Differential Source Follower Buffer for High-PSRR Bandwidth
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Solution Overview
Problem
Existing buffers face challenges in maximizing performance parameters such as noise rejection, bandwidth, and power consumption, particularly in high-bandwidth time-interleaved analog-to-digital converters, where they suffer from low power supply rejection ratio (PSRR) and feedback-induced memory effects (FME), leading to inter-symbol interference (ISI).
Innovation Solution
A differential source follower-based buffer architecture is introduced, incorporating current steering devices and capacitors to improve PSRR and reduce FME, featuring a bias generator for optimal biasing and a differential class AB source follower configuration that enhances bandwidth and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If existing buffer architectures are used to provide high bandwidth, then signal propagation speed is improved, but power supply rejection ratio (PSRR) deteriorates and feedback-induced memory effects (FME) increase
Solution Approach 1:
The buffer is divided into multiple independent source follower stages, each with its own current steering device. This segmentation allows each stage to operate independently with optimized bandwidth and PSRR characteristics, preventing the feedback-induced memory effects that occur in monolithic buffer designs.
Solution Approach 2:
Current steering devices are introduced as intermediary elements between the differential source follower stages. These current steering devices act as mediators that control signal flow and isolate stages from each other, improving PSRR by preventing power supply noise propagation while maintaining high bandwidth through efficient current switching.
2Speed
If existing buffer architectures are used to provide high bandwidth, then signal propagation speed is improved, but inter-symbol interference (ISI) increases
Solution Approach 1:
The buffer architecture segments the signal path into multiple independent source follower stages. This segmentation prevents the accumulation of feedback-induced memory effects that cause inter-symbol interference, while each stage maintains high bandwidth performance for fast signal propagation.
Solution Approach 2:
The differential source follower configuration with current steering devices implements a form of negative feedback that cancels out memory effects. The differential structure ensures that feedback signals counteract the feedback-induced memory effects, thereby reducing inter-symbol interference while preserving bandwidth.
3Reliability
If buffer size is increased to improve noise rejection, then power supply rejection ratio is improved, but power consumption increases
Solution Approach 1:
The buffer is segmented into multiple low-power source follower stages rather than using a single large buffer. Each stage consumes minimal power while collectively providing superior noise rejection through the cumulative effect of multiple differential stages with current steering isolation.
Solution Approach 2:
The differential source follower stages with current steering devices are self-biasing, automatically adjusting their operating points to optimize the trade-off between noise rejection and power consumption. The current steering devices self-regulate the current flow to maintain high PSRR without requiring excessive power.
Data Source
AI summary
Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.