Source Follower Circuit With Self-Biased MOS Load for Stable DC Bias
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Solution Overview
Problem
Existing source follower circuits with local negative feedback loops face instability in DC bias and limited bias flexibility, particularly in modern CMOS processes, necessitating a more efficient and stable circuit design.
Innovation Solution
A source follower circuit incorporating a self-biased diode-connected MOS load and a feedback loop, utilizing a low-pass filter and reference current generator to stabilize DC bias and enhance linearity and driving capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a local negative feedback loop is formed with a floating capacitor to improve bias flexibility, then bias flexibility is improved, but DC bias stability deteriorates
Solution Approach 1:
The patent introduces a self-biased diode-connected MOS transistor as an intermediary component between the feedback loop and the amplifying transistor. This intermediary provides a stable DC bias voltage at the internal node by acting as a voltage reference, while still allowing the floating capacitor to provide AC feedback for improved bias flexibility. The diode-connected MOS transistor effectively mediates between the conflicting requirements of DC stability and AC flexibility.
2Device complexity
If a direct current (DC) coupling path is used for the feedback loop to simplify the circuit, then circuit simplicity is improved, but linearity deteriorates in modern CMOS processes
Solution Approach 1:
The patent segments the feedback coupling into AC and DC components. The floating capacitor handles AC feedback signals to maintain linearity in modern CMOS processes, while the self-biased diode-connected MOS transistor separately provides DC bias stabilization. This segmentation allows each component to optimize its specific function without compromising the other, resolving the contradiction between simplicity and linearity.
3Adaptability or versatility
If the feedback loop is implemented with a floating capacitor to improve bias flexibility, then bias flexibility is improved, but output impedance reduction is compromised
Solution Approach 1:
The patent employs a feedback mechanism where the self-biased diode-connected MOS transistor continuously monitors and adjusts the DC bias voltage at the internal node. This feedback ensures that the output impedance remains low and stable while the floating capacitor provides the necessary AC feedback path for bias flexibility. The feedback loop dynamically balances both requirements.
Data Source
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AI summary
A source follower circuit (100) includes a first MOS transistor (M1), a second MOS transistor (M2), a third MOS transistor (M3), and a feedback loop circuit (104). Regarding the first MOS transistor (M1), a gate terminal receives an input signal (VIN), and a source terminal outputs an output signal (VOUT). Regarding the second MOS transistor (M2), a gate terminal is coupled to a bias voltage (VB), a source terminal is coupled to a first reference voltage (VDD), and a drain terminal is coupled to the source terminal of the first MOS transistor (M1). Regarding the third MOS transistor (M3), it is a self-biased diode-connected MOS transistor. The drain terminal of the third MOS transistor (M3) is coupled to a drain terminal of the first MOS transistor (M1), and a source terminal of the third MOS transistor (M3) is coupled to a second reference voltage (GND).