Source Line Compensation Plug for Low-Resistance Memory Contacts

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Solution Overview

Problem

Current memory devices face challenges in reducing resistance between the source line and cell plug, and preventing physical defects of the source line exposed during the etching process for forming landing holes, which can deteriorate electrical characteristics.

Innovation Solution

A memory device with a compensation plug containing a higher concentration of impurities than the source line, formed below the cell plug, to reduce resistance and prevent physical defects by enhancing the electrical characteristics of the source line.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the source line is formed with standard impurity concentration, then the manufacturing process is simple, but the resistance between the source line and cell plug is high

Engineering Contradiction:
Improveelectrical characteristicsVSAvoidstructure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by forming a compensation plug with high impurity concentration specifically at the landing hole region where the source line contacts the cell plug, while the rest of the source line maintains standard impurity concentration. This localized modification reduces resistance at the critical contact point without unnecessarily complicating the entire source line structure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the impurity concentration parameter locally by forming the compensation plug with higher impurity concentration than the standard source line. This parameter change directly addresses the high resistance issue at the source line-cell plug interface, improving electrical characteristics through controlled modification of material properties in the critical region.

Inventive Principle:
Principle #35Parameter changes

2Ease of operation

If the source line is etched to form landing holes, then the cell plug can contact the source line, but the source line may suffer physical defects during etching

Engineering Contradiction:
Improvecontact formationVSAvoidsource line integrity
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent applies beforehand cushioning by forming the compensation plug with high impurity concentration in advance, before the etching process that creates landing holes. This pre-formed compensation plug acts as a buffer that protects the source line from physical defects during subsequent etching operations, ensuring source line integrity while still enabling proper contact formation.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The compensation plug serves as an intermediary element between the source line and the cell plug. It mediates the interaction by providing a robust, high-conductivity contact region that can withstand the etching process while ensuring reliable electrical connection, thus protecting the source line from direct exposure to harsh etching conditions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The compensation plug effectively reduces resistance between the source line and cell plug, preventing physical defects and improving the electrical characteristics of the memory device.

Implementation Method 1

the compensation plug contains an impurity that has a higher concentration than an impurity that is contained in the source line

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS20230299006A1Memory device and manufacturing method of the memory device
Publication Date: 2023.09.21 SK HYNIX INC
  • US20230299006A1 patent drawing
  • US20230299006A1 patent drawing
  • US20230299006A1 patent drawing

AI summary

There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a source line; a stack structure formed on the source line; a cell plug penetrating the stack structure and contacting the source line; a slit separating the stack structure; a source contact formed in the slit, the source contact in contact with the source line; and a compensation plug formed below the cell plug in the source line, wherein the compensation plug contains an impurity that has a higher concentration than an impurity that is contained in the source line.