Flash Memory Source Line Etch to Avoid Photoresist Scum
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Solution Overview
Problem
The formation of high resistance connections between contact vias and source lines in flash memory devices due to photoresist scum, leading to device failure and shifts in operating parameters, is a challenge in bulk manufacturing.
Innovation Solution
An enhanced etch method that omits the second mask and extends the first etch through the source dielectric layer to expose the source line, reducing the risk of photoresist scum and using one less photomask, thereby improving the process window for forming silicide layers and contact vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a second mask is used to open the source line, then the source line can be exposed, but photoresist scum forms on the source line causing high resistance connections
Solution Approach 1:
The patent removes the second mask step from the manufacturing process entirely. Instead of using a second photomask to open the source line, the method extends the first etch process to also open the source line through the source dielectric layer, extracting the harmful second mask application step that causes photoresist scum formation.
Solution Approach 2:
The patent combines the function of opening the erase gate line and opening the source line into a single etch process. By extending the first etch to penetrate through the source dielectric layer, the method merges two separate operations (opening erase gate and opening source line) into one unified process, eliminating the need for a second mask.
2Manufacturing precision
If multiple photomasks are used in the process, then precise patterning can be achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the patterning functions of multiple photomasks into a single photomask (the first mask). The first mask is used to define both the erase gate opening and the source line opening, consolidating what previously required separate masks into one unified patterning step, thereby reducing manufacturing complexity.
Solution Approach 2:
The first photomask is given multiple functions: it patterns both the erase gate line opening and the source line opening. This multi-functional use of a single mask reduces the total number of masks required while maintaining the necessary patterning precision for both features.
3Ease of manufacture
If the first etch is extended through the source dielectric layer, then the source line is exposed without a second mask, but the etch process becomes more aggressive
Solution Approach 1:
The patent applies local quality by using different etch selectivities for different layers. The etch process is designed to have high selectivity for the erase gate line material and the source dielectric layer, allowing the first etch to penetrate through the source dielectric to expose the source line while maintaining control over the etching depth and preventing over-etching into the substrate.
Solution Approach 2:
The patent changes the etch parameters (such as etch chemistry, power, pressure, and time) to achieve the desired etch depth through the source dielectric layer while maintaining precision. By optimizing these parameters, the extended etch process can expose the source line effectively without compromising manufacturing control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces the likelihood of high resistance connections and enhances manufacturing yields by enlarging the process window for forming silicide layers and contact vias, leading to improved device performance and cost savings from reduced photomask usage.
Implementation Method 1
An enhanced etch method that omits the second mask and extends the first etch through the source dielectric layer to expose the source line
Data Source
AI summary
Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.