Source Line Plane for Floating Body Memory Charge Retention

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Solution Overview

Problem

Conventional reading and writing techniques for semiconductor memory devices with electrically floating bodies suffer from inefficiencies, including the need for numerous voltage drivers that occupy significant space and cause charge loss due to charge pumping, which reduces the net charge representing data over time.

Innovation Solution

The implementation of a source line plane coupled to a constant voltage source, which eliminates individual source line drivers and provides a comprehensive voltage potential to memory cells, reducing the need for multiple drivers and minimizing charge loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If conventional reading and writing techniques are used with individual source line drivers, then voltage control for memory cells is achieved, but the area occupied by voltage drivers increases and charge loss occurs

Engineering Contradiction:
Improvearea occupied by voltage driversVSAvoidcharge retention in memory cells
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

Multiple individual source line drivers are merged into a single source line plane that provides voltage to multiple memory cells simultaneously. This consolidation reduces the total area occupied by driver circuitry while eliminating the charge pumping effect that occurs with individual drivers switching between positive and negative gate biases.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The source line plane serves multiple functions: it provides voltage control to multiple memory cells, maintains stable charge states, and eliminates the need for individual drivers. This multi-functional approach reduces overall system complexity and improves charge retention across all connected memory cells.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If pulsing between positive and negative gate biases is used during read and write operations, then data writing and reading is enabled, but charge pumping occurs that reduces net charge representing data

Engineering Contradiction:
Improvedata reading and writing capabilityVSAvoidnet charge representing data
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

The source line plane acts as an intermediary between the voltage drivers and the memory cells, providing a stable reference potential that prevents charge pumping. By serving as a common voltage reference for multiple cells, it enables read and write operations without the harmful charge loss that occurs when individual drivers pulse gates between positive and negative biases.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Stability of the object's composition

If a source line plane coupled to a constant voltage source is implemented, then charge state stability is improved, but the structure becomes more complex

Engineering Contradiction:
Improvecharge state stability in memory cellsVSAvoidstructure of voltage supply system
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The constant voltage source is extracted as a separate, dedicated component that exclusively supplies the source line plane. This extraction simplifies the overall system by providing a stable reference potential without requiring complex control circuitry, as the constant voltage source inherently maintains stable operation without additional regulation.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS8319294B2Techniques for providing a source line plane
Publication Date: 2012.11.27 MICRON TECHNOLOGY INC
  • US8319294B2 patent drawing
  • US8319294B2 patent drawing
  • US8319294B2 patent drawing

AI summary

Techniques for providing a source line plane are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for providing a source line plane. The apparatus may comprise a source line plane coupled to at least one constant voltage source. The apparatus may also comprise a plurality of memory cells arranged in an array of rows and columns, each memory cell including one or more memory transistors. Each of the one or more memory transistors may comprise a first region coupled to the source line plane, a second region coupled to a bit line, a body region disposed between the first region and the second region, wherein the body region may be electrically floating, and a gate coupled to a word line and spaced apart from, and capacitively coupled to, the body region.