Parallel Source-Line Tracks for Uniform Memory Read Currents
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Solution Overview
Problem
The unbalanced sheet resistance between bit lines and source lines in memory devices leads to varying read currents for memory cells in the same column, causing inconsistencies in data reading.
Innovation Solution
Connecting multiple source line metal tracks in parallel to reduce sheet resistance and balance the resistance between bit lines and source lines, determined by a method based on the sheet resistance of both types of tracks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple source line metal tracks are connected in parallel, then sheet resistance is reduced and read current balance is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The source line is segmented into multiple parallel metal tracks instead of using a single thick track. Each track carries a portion of the total current, and their parallel connection achieves the desired current balance with standard-thickness metal layers, resolving the contradiction between reliability improvement and device complexity
Solution Approach 2:
Multiple thin metal tracks are merged in parallel to functionally equivalent a single thick metal track. This combining approach achieves the low resistance required for read current balance while using available standard metal layer thicknesses, thus improving reliability without requiring non-standard manufacturing processes
2Area of stationary object
If source line metal tracks are made thinner with smaller pitch, then area is reduced, but sheet resistance increases causing read current imbalance
Solution Approach 1:
Instead of using a single thick metal track that occupies large area, the source line is segmented into multiple parallel tracks with smaller individual cross-sections. The combined effect of multiple tracks in parallel achieves the required low resistance while maintaining compact area, thus resolving the contradiction between area reduction and read current consistency
Solution Approach 2:
The design changes the geometric parameters of the metal tracks by using multiple tracks with optimized width and spacing. By adjusting the number of parallel tracks and their individual dimensions, the patent achieves the target sheet resistance value while minimizing total area, thereby improving both area efficiency and read current consistency
Data Source
AI summary
A memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, each row of memory cells being associated with a word line, each column of memory cells being associated with a bit line and a source line. Each memory cell includes: a storage device coupled to the bit line, the storage device being selectable between a first resistance state and a second resistance state in response to a bit line signal at the bit line; and a selection device connected in series with the storage device and coupled to the source line, the selection device being configured to provide access to the storage device in response to a word line signal at the word line. The memory device further includes a word-line driver and a bit-line driver. A first number of the source lines are connected in parallel.