Conductive Source Line Sidewall Contact for 3D NAND
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Solution Overview
Problem
Three-dimensional vertical NAND strings face challenges with high electrical resistance and variable resistance due to substrate-based source lines, leading to reduced cell read current and increased noise, and require complex and time-consuming fabrication processes.
Innovation Solution
A method for forming a NAND memory cell region with a conductive source line parallel to the substrate, where the semiconductor channel contacts only the sidewall of the source line, reducing resistance and noise, and using a self-aligned process integration for efficient fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a substrate with high electrical resistance is used as the source line, then the substrate can be used directly without additional conductive layers, but the cell read current is reduced and source line noise is increased
Solution Approach 1:
The source line is segmented into two functional parts: a conductive source line layer (separate from the substrate) that provides low-resistance electrical connection, and the substrate that serves as the foundation. This segmentation allows each component to optimize its function - the conductive layer provides low resistance while the substrate provides structural support.
Solution Approach 2:
A conductive source line layer is introduced as an intermediary between the substrate and the memory openings. This intermediary layer mediates the electrical connection, providing low resistance paths while allowing the substrate to remain as the base structure. The conductive source line layer acts as a mediator that resolves the conflict between substrate simplicity and electrical performance requirements.
2Manufacturing precision
If memory openings are formed by repeated formation and etching processes, then the active regions can be precisely defined, but the fabrication process becomes time-consuming and complex
Solution Approach 1:
The source line layer is formed preliminarily before the memory openings are created. This preliminary formation of the conductive source line layer simplifies subsequent processing steps, as the low-resistance connection is already in place before etching the memory openings, reducing the need for repeated formation and etching cycles.
Solution Approach 2:
Multiple functions are merged into fewer process steps. The source line formation is combined with the substrate preparation in a way that the conductive layer is deposited and patterned in integration with the memory opening formation, reducing the total number of separate formation and etching cycles required.
3Reliability
If the semiconductor channel contacts only the sidewall of the source line, then resistance is reduced and noise is reduced, but the fabrication alignment requirements become more stringent
Solution Approach 1:
The structure is designed to be self-aligning during fabrication. The semiconductor channel naturally contacts the sidewall of the conductive source line through conformal deposition processes, where the channel material deposits on the sidewalls of the memory openings that are formed over the source line. This self-service alignment mechanism reduces the need for additional alignment steps while achieving the desired sidewall contact geometry.
Solution Approach 2:
The contact geometry transitions from a planar interface to a three-dimensional sidewall contact. By having the semiconductor channel contact the vertical sidewall of the conductive source line rather than a horizontal interface, the design achieves better electrical performance while the vertical dimension provides natural alignment through the depth of the memory openings.
4Reliability
If a conductive source line layer is added over the substrate, then electrical resistance is reduced and cell current is improved, but the device structure becomes more complex
Solution Approach 1:
The conductive source line layer serves multiple functions simultaneously: it provides low-resistance electrical connection, acts as a barrier layer preventing diffusion, and serves as a foundation for subsequent memory opening formation. This multi-functionality reduces the need for additional separate layers or structures, thereby limiting the increase in overall device complexity while achieving improved electrical performance.
Data Source
Figure 1A~1D
Figure 1E~1F
Figure 2A~2C
AI summary
A NAND memory cell region of a NAND device includes a conductive source line that extends substantially parallel to a major surface of a substrate, a first semiconductor channel that extends substantially perpendicular to a major surface of the substrate, and a second semiconductor channel that extends substantially perpendicular to the major surface of the substrate. At least one of a bottom portion and a side portion of the first semiconductor channel contacts the conductive source line and at least one of a bottom portion and a side portion of the second semiconductor channel contacts the conductive source line.