Source Line Voltage Adjustment for Neighbor Select Gate Interference
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Solution Overview
Problem
Semi-circle drain side select gate (SC-SGD) memory technology faces inefficiencies due to the removal of metal layers during etching, leading to parasitic transistor leakage and program failures during memory operations, as unselected SC-SGDs can be partially turned on by neighboring select gate voltages.
Innovation Solution
A memory apparatus and method that apply specific select gate voltages and source line voltages to selected memory holes, with a control means to count conducting cell quantities during read operations and adjust the source line voltage based on the relationship between these quantities and a predetermined threshold, thereby mitigating the interference effects and improving operational reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If etching technology is used to create semi-circular memory holes, then die size is reduced, but parasitic transistor leakage occurs due to removal of shielding metal layers
Solution Approach 1:
The patent applies preliminary anti-action by compensating for the harmful effect of neighbor drain side select gate interference before it causes program failures. The control means adjusts the source line voltage based on detected conducting cell quantities to preemptively counteract the parasitic leakage effect, ensuring reliable programming despite the structural vulnerability created by the semi-circular etching design.
2Ease of operation
If select gate voltage is applied to selected drain side select gate, then memory operation is enabled, but unselected SC-SGD is partially turned on causing program failures
Solution Approach 1:
The patent implements feedback by detecting the quantity of conducting cells during read operations and using this information to adjust the source line voltage for subsequent programming operations. This closed-loop control mechanism allows the system to adapt to the actual electrical conditions and compensate for neighbor drain side select gate interference, maintaining both operational capability and programming reliability.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the source line voltage based on the detected conducting cell quantity. The control means modifies the voltage parameter to compensate for the interference effect, thereby maintaining reliable memory operation despite the presence of unselected SC-SGD transistors that are partially turned on.
3Reliability
If source line voltage is adjusted based on conducting cell quantity, then program failures are reduced, but additional control complexity is introduced
Solution Approach 1:
The patent applies self-service by enabling the memory system to automatically detect and compensate for its own interference problems. The control means monitors conducting cell quantities and autonomously adjusts the source line voltage without requiring external intervention or complex additional control circuitry, allowing the system to self-correct the parasitic leakage issue.
Data Source
AI summary
A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes. The memory cells are connected in series between a drain-side select gate transistor on a drain-side and connected to one of a plurality of bit lines and a source line on a source-side. A control means is configured to apply a first and a second select gate voltage to the drain-side select gate transistor while applying a predetermined source line voltage to the source line of selected ones of the memory holes in a predetermined grouping and a read level voltage to at least one of the word lines associated with the predetermined grouping. The control means counts the memory cells conducting during each of a first and a second read operation and adjusts the predetermined source line voltage accordingly.