Source Line Width Variation for Resistance Change Memory Read Stability

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Solution Overview

Problem

Miniaturization of resistance change memory cells leads to variations in source potential of select transistors, causing read and write errors due to changes in resistance of source lines, which affect the read and write currents.

Innovation Solution

Increasing the width or thickness of source lines relative to bit lines or gradually varying the thickness of source lines to reduce resistance variations, thereby stabilizing the source potential and minimizing read and write errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the memory cell is miniaturized to increase storage density, then the storage capacity is improved, but the source line resistance increases causing source potential variation and read/write errors

Engineering Contradiction:
Improvestorage densityVSAvoidread/write accuracy
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent changes the physical parameters of the source line by increasing its width or thickness, which directly modifies the resistance parameter to compensate for the increased resistance caused by miniaturization. This parameter adjustment ensures that the source potential remains stable across different memory cell positions, thereby maintaining read/write accuracy while enabling higher storage density

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies preliminary compensation by adjusting the source line dimensions before the read/write operations occur. By pre-establishing the appropriate source line geometry (wider or thicker), the design anticipates and counteracts the resistance effects that would otherwise cause potential variation and errors during operation

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If the source line resistance is increased due to miniaturization, then the storage density is improved, but the source potential varies according to memory cell position causing read/write errors

Engineering Contradiction:
Improvestorage densityVSAvoidsource potential stability
Core Design Contradiction:
Quantity of substanceVSStability of the object's composition

Solution Approach 1:

The patent modifies the source line's physical parameters (width or thickness) to change its resistance characteristic. This parameter change compensates for the position-dependent potential variation, ensuring that the source potential remains stable across all memory cell positions in the miniaturized array, thus maintaining both high storage density and potential stability

Inventive Principle:
Principle #35Parameter changes

3Stability of the object's composition

If the source line dimensions are increased to reduce resistance, then the source potential stability is improved, but the device complexity increases

Engineering Contradiction:
Improvesource potential stabilityVSAvoidline structure complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The patent applies local quality by making the source line dimensions non-uniform - specifically, positioning wider or thicker sections at critical locations where potential variation occurs most. This localized modification approach reduces resistance and stabilizes source potential only where needed, rather than uniformly increasing all source line dimensions, thereby minimizing the overall increase in device complexity

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10311929B2Resistance change memory
Publication Date: 2019.06.04 SK HYNIX INC
  • US10311929B2 patent drawing
  • US10311929B2 patent drawing
  • US10311929B2 patent drawing

AI summary

According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.