Source Mask Optimization via Layout Pattern Grouping

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Solution Overview

Problem

Current source mask optimization techniques are computationally intensive and can take years to complete, making it impractical to perform on entire integrated circuit designs, leading to reduced manufacturing yields due to pattern-dependent defects in smaller feature sizes.

Innovation Solution

The method involves analyzing the layout design by identifying and consolidating sections with similar patterns into groups, classifying their compatibility with the optical lithographic process using a cost function, and optimizing sections difficult to print through source mask optimization, while applying conventional resolution enhancement to the entire design.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If source mask optimization is performed on entire integrated circuit designs, then manufacturing precision is improved, but computation time becomes excessively long (years)

Engineering Contradiction:
Improvefidelity of optical lithographic processVSAvoidcomputation time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The layout design is divided into multiple sections, each processed independently through the optimization workflow. Pattern recognition groups similar sections together, allowing the system to process representative patterns rather than every individual geometry, thereby reducing overall computation time while maintaining manufacturing precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Pattern recognition and classification are performed in advance to identify difficult-to-print patterns before the main optimization process. This preliminary analysis allows the system to focus computational resources only on critical sections that require optimization, rather than processing the entire design uniformly.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If computational resources are increased to perform full design optimization, then manufacturing precision improves, but cost and resource requirements become prohibitive

Engineering Contradiction:
Improveoptimization fidelityVSAvoidcomputational resources
Core Design Contradiction:
Manufacturing precisionVSUse of energy by moving object

Solution Approach 1:

The system applies different levels of optimization to different sections of the layout based on their printability characteristics. Difficult-to-print patterns identified through pattern recognition receive full optimization treatment, while easier patterns use standard processes, thereby reducing overall computational resource requirements while maintaining manufacturing precision for critical features.

Inventive Principle:
Principle #3Local quality

3Measurement precision

If layout sections are processed individually, then optimization accuracy is maintained, but processing time increases significantly

Engineering Contradiction:
Improveoptimization accuracyVSAvoidprocessing speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

Layout sections with similar patterns are grouped together and processed as representative samples. By merging similar sections into pattern groups, the system maintains optimization accuracy for each unique pattern type while significantly reducing the total number of processing operations required, thereby improving productivity without sacrificing precision.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9418195B2Layout content analysis for source mask optimization acceleration
Publication Date: 2016.08.16 SIEMENS INDUSTRY SOFTWARE INC
  • US9418195B2 patent drawing
  • US9418195B2 patent drawing
  • US9418195B2 patent drawing

AI summary

The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the layout design having similar patterns are identified and consolidated into pattern groups. Subsequently, sections of the layout design corresponding to the pattern groups may be analyzed to determine their compatibility with the optical lithographic process, and the compatibility of these sections may be classified based upon a “cost function.” With further implementations, the analyzed sections may be classified as printable or difficult to print, depending upon the particular lithographic system. The compatibility of various sections of a layout design may then be utilized to optimize the layout design during a lithographic friendly design process. For example, during the design phase, sections categorized as difficult to print may be flagged for further optimization, processing, or redesign. In further implementations, the difficult-to-print sections may be subjected to a source mask optimization process. Subsequently, the entire layout design may receive a conventional resolution enhancement treatment using the optimized source.