Source Mask Optimization Using Critical Pattern Selection
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Solution Overview
Problem
Current lithographic processes face challenges in optimizing illumination sources and masks for full-chip designs, particularly for complex layouts, leading to high computational costs and inefficiencies in achieving optimal process windows, especially for designs beyond simple repeating patterns like memory designs.
Innovation Solution
The method involves selecting a small set of critical design patterns from the full set of clips, optimizing the illumination source for these patterns, and using the optimized source to enhance the mask design, thereby reducing computational costs and improving process window performance through iterative convergence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional full-chip source and mask optimization methods are used, then process window performance is improved, but computational cost increases significantly
Solution Approach 1:
The full-chip design is segmented into multiple clips, and the clips are further grouped into clusters based on pattern similarity. Optimization is performed on representative clips from each cluster rather than all clips, reducing computational complexity while maintaining coverage of diverse patterns across the full chip.
Solution Approach 2:
Instead of optimizing each individual clip, the method uses representative clips from clusters to generate optimized sources and masks. These optimized solutions are then copied and applied to other clips within the same cluster, achieving full-chip optimization with significantly reduced computational effort.
2Manufacturing precision
If optimization is performed on all full-chip patterns, then comprehensive pattern coverage is achieved, but processing time increases
Solution Approach 1:
The method performs preliminary grouping of clips into clusters based on pattern similarity before optimization. This preliminary action identifies representative clips that capture the diversity of the full chip, allowing optimization to focus on these representatives and thereby reducing processing time while maintaining comprehensive pattern coverage.
Solution Approach 2:
Instead of performing exhaustive optimization on all clips, the method applies partial optimization to a selected subset of representative clips from each cluster. This partial action is sufficient to achieve good process window performance across the full chip without the excessive processing time required for complete optimization.
3Productivity
If a simplified optimization approach is used, then computational cost is reduced, but process window performance deteriorates
Solution Approach 1:
The method changes the parameter of optimization scope from individual clips to cluster-level representatives. By adjusting this parameter, the approach achieves a balance between computational efficiency and process window performance, as the representative clips capture the essential pattern diversity needed for good lithographic results.
Solution Approach 2:
The optimization process uses feedback from aerial image simulations and process window calculations on representative clips to refine the selected subset of clips. This feedback mechanism ensures that the simplified approach maintains or improves process window performance by iteratively identifying the most critical patterns for optimization.
Data Source
AI summary
The present invention relates to lithographic apparatuses and processes, and more particularly to tools for co-optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.