Source Ordering in PCIe/CXL Interconnects via Non-Default Virtual Channels
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Solution Overview
Problem
Existing interconnect architectures in computing systems face challenges in managing high-performance communication demands, particularly in non-tree structures and peer-to-peer applications, leading to inefficiencies such as storage and power consumption issues, as well as limitations in supporting diverse market segments like servers and mobile ecosystems.
Innovation Solution
Implementing source ordering rules in device interconnects, specifically through the use of non-default virtual channels (VCs) in PCIe- or CXL-based systems, allowing for enhanced flow control and transaction ordering to optimize bandwidth and reduce power consumption by enabling direct memory access without relying on root ports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional multi-drop buses are used for interconnect architecture, then electrical communication is simplified, but communication speed and performance are limited
Solution Approach 1:
The patent segments the interconnect architecture into multiple virtual channels (VCs) that operate independently. Each VC can handle transactions separately, allowing parallel communication paths that increase overall bandwidth and speed while maintaining manageable complexity through modular organization.
Solution Approach 2:
The patent introduces a new dimension to the interconnect architecture by adding virtual channel differentiation. Instead of a single flat communication path, transactions are routed through multiple dimensional layers (VC0, VC1, VC2, etc.), enabling simultaneous multi-path communication that dramatically increases speed without proportionally increasing physical complexity.
2Productivity
If root ports are used for memory access, then system compatibility is maintained, but bandwidth utilization and power efficiency are reduced
Solution Approach 1:
The patent extracts the memory access function from the traditional root port path and creates dedicated peer-to-peer transaction paths through alternative virtual channels. This separation allows direct memory access without routing through root ports, eliminating unnecessary hops that consume power and reduce bandwidth efficiency.
Solution Approach 2:
The patent introduces alternative virtual channels as intermediary paths for memory transactions. These VCs act as mediators that enable direct peer-to-peer communication between devices and memory, bypassing the root port intermediary that traditionally handled all memory access, thereby improving both bandwidth and power efficiency.
3Reliability
If transaction ordering is not enforced, then communication latency is reduced, but data integrity and consistency are compromised
Solution Approach 1:
The patent applies different ordering rules to different virtual channels based on local quality requirements. VC0 maintains strict ordering for reliability-critical transactions, while other VCs may use relaxed ordering for latency-sensitive applications. This localized approach to ordering ensures data consistency where needed without imposing unnecessary latency constraints elsewhere.
Data Source
AI summary
In one embodiment, an apparatus includes a port to transmit and receive data over a link; and protocol stack circuitry to implement one or more layers of a load-store input/output (I/O)-based protocol (e.g., PCIe or CXL) across the link. The protocol stack circuitry constructs memory write request transaction layer packets (TLPs) for memory write transactions, wherein fields of the memory write request TLPs indicate a virtual channel (VC) other than VC0, that a completion is required in response to the memory write transaction, and a stream identifier associated with the memory write transaction. The memory write request TLP is transmitted over the link and a completion TLP is received over the link in response, indicating a completion for the memory write request TLP.