Source Side Precharge Control for NAND Memory Error Reduction
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Solution Overview
Problem
Reverse order programming (ROP) methods in three-dimensional memory arrays result in a wider upper tail of threshold voltage distribution for the erased state, leading to increased errors where cells are read as programmed instead of erased, particularly in lower word lines, due to the source-side precharging mechanism.
Innovation Solution
A die controller is configured to manage the source-side select gate discharge during the precharge stage, ensuring the channel maintains an electrical path and mitigates potential gradients, thereby preventing unintended changes in threshold voltage of erased cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If source-side precharging is used in reverse order programming, then programming speed is improved, but threshold voltage distribution for erased state becomes broader
Solution Approach 1:
The patent segments the precharging operation into two distinct phases: a first precharge phase that charges the channel to a first potential, and a second precharge phase that charges the channel to a second potential. This segmentation allows different precharge levels to be applied at different stages of the reverse order programming process, thereby maintaining programming speed while controlling the broadening of threshold voltage distribution in the erased state.
2Productivity
If source-side precharging is used in reverse order programming, then programming efficiency is improved, but bit error rate increases
Solution Approach 1:
The patent applies preliminary action by performing the first precharge phase before the second precharge phase. The first precharge phase prepares the channel by charging it to a first potential, and then a second precharge phase charges it to a second potential. This preliminary sequencing of precharge operations allows the system to maintain programming efficiency while preventing the threshold voltage broadening that would otherwise increase bit error rates in the erased state.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the occurrence of cells being mistakenly read as programmed, improving the accuracy of the erased state by maintaining the precharge potential and inhibiting programming errors in unselected memory cells.
Implementation Method 1
A die controller is configured to manage the source-side select gate discharge during the precharge stage, ensuring the channel maintains an electrical path and mitigates potential gradients
Implementation Method 2
During programming, unselected word lines are inhibited by boosting them to a higher voltage potential, and the precharge stage allows this boost to begin at a higher potential rather than having to boost up from a lower or zero potential
Data Source
AI summary
This disclosure relates to apparatuses and a method for retaining a bias in a NAND string channel during source-side precharge. The apparatuses include a memory array and a die controller configured to mitigate formation of a potential gradient in the channel of the memory array NAND strings during a program storage operation. To this end, a plurality of source-side select gates is activated, then each of the plurality of source side dummy word line select gates is activated. Next, a NAND string channel is biased by biasing the source line coupled to the NAND string by the plurality of source-side select gates. Finally, the plurality of source-side select gates and the plurality of source side dummy word line select gates are discharged such that the channel maintains an electrical path to the source line.