3D Memory Cell Stack With Source Protrusion for GIDL Erase
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Solution Overview
Problem
Current integrated circuit devices face limitations in increasing data storage capacity and electrical properties, particularly in generating gate-induced drain leakage (GIDL) current efficiency during erase operations.
Innovation Solution
The integration of a source protrusion pattern and pad pattern within the channel structures, which include a core insulating layer, channel layer, and gate dielectric layer, allows for increased GIDL current generation by overlapping erase control gate electrodes, thereby enhancing electrical properties and data storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar memory cell structures are used, then manufacturing simplicity is maintained, but data storage capacity and electrical properties deteriorate
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked vertically with gate electrodes arranged in multiple levels, enabling increased storage capacity per unit area while maintaining manufacturability through established semiconductor fabrication processes adapted for 3D structures.
Solution Approach 2:
The patent implements nested structures where channel structures are surrounded by gate dielectric layers, which are in turn surrounded by gate electrodes. Multiple gate electrode layers are nested vertically, with each layer containing and protecting the elements below it, creating a compact multi-layer configuration that maximizes storage density.
2Productivity
If erase control gate electrodes are configured to maximize GIDL current generation area, then erase operation efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The erase control function is divided into multiple separate gate electrode layers (first erase control gate electrode and second erase control gate electrode) positioned at different vertical levels. Each gate electrode can be independently controlled and optimized, allowing GIDL current to be generated across multiple areas simultaneously, thereby improving overall erase efficiency while maintaining manageable manufacturing tolerances for each individual layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the efficiency of GIDL current generation during erase operations, increasing the area of current generation and thus enhancing the electrical properties and data storage capabilities of integrated circuit devices.
Implementation Method 1
generating gate-induced drain leakage (GIDL) current efficiency during erase operations
Data Source
AI summary
An integrated circuit device includes a semiconductor substrate, and a common source structure on the substrate. A vertical stack of memory cell gate electrodes is provided, which extends between the common source structure and the substrate. The vertical stack of memory cell gate electrodes includes a first erase control gate electrode, and a plurality of word lines extending between the first erase control gate electrode and the substrate. At least one channel structure is provided, which vertically penetrates through the vertical stack of memory cell gate electrodes. A source protrusion pattern is provided, which is electrically connected to the common source structure. The source protrusion pattern extends sufficiently through the vertical stack of memory cell gate electrodes that a portion of the source protrusion pattern extends opposite a sidewall of the first erase control gate electrode.