Source Select Transistor Floating for Memory Precharge
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Solution Overview
Problem
Memory devices face inefficiencies in the source line precharge operation during programming, leading to increased loading and reduced speed, and in erase operations, where the threshold voltage distribution of source select transistors is affected by GIDL voltage.
Innovation Solution
The memory device floats some source select transistors adjacent to the source line during precharge operations and applies varying erase voltages to manage the GIDL voltage, reducing capacitance and improving operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If all source select transistors are kept connected during source line precharge operation, then the source line can be fully precharged, but the loading of the source line increases and precharge speed decreases
Solution Approach 1:
The source select transistors are divided into two groups: some are floated (disconnected) while others remain connected to the source line. This segmentation allows the source line to be precharged through only a subset of transistors, reducing the total capacitance that needs to be charged and thereby improving precharge speed while managing the loading effectively.
Solution Approach 2:
Different source select transistors are assigned different states (floating vs. connected) based on their specific positions and functional requirements. This local differentiation optimizes the precharge operation by connecting only the necessary transistors to the source line, reducing unnecessary capacitive loading while ensuring adequate precharge coverage.
2Productivity
If erase voltage is applied to source line during erase operation, then the erase operation can proceed, but GIDL voltage affects the threshold voltage distribution of source select transistors
Solution Approach 1:
Source select transistors are floated before applying the erase voltage to the source line. This preliminary action prevents the GIDL voltage from affecting the threshold voltage distribution of the source select transistors during the erase operation, thereby maintaining their electrical characteristics while still enabling efficient erase operation through the memory cells.
Data Source
AI summary
A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.