Source Separated Cell MOS Device Parallel Current Paths
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Solution Overview
Problem
Reducing the size and area footprint of ASICs increases resistance in current paths within MOS devices, leading to increased IR-drop and potential timing issues in digital logic circuits.
Innovation Solution
The implementation of a MOS device with a specific layout construction that includes multiple MOS transistors with separate source connections and floating gates, reducing effective resistance by using parallel current paths, thereby minimizing IR-drop and improving timing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the size and area footprint of ASICs is reduced, then the area occupied by the circuit is decreased, but the resistance in current paths increases
Solution Approach 1:
The patent segments the current path by introducing multiple parallel current paths between the first and second voltage sources. Instead of a single current path with high resistance, the circuit divides current flow through multiple transistors (first, second, third, fourth, fifth, and sixth MOS transistors) arranged in parallel configurations, thereby reducing the effective resistance while maintaining a compact area footprint.
2Area of stationary object
If the size and area footprint of ASICs is reduced, then the area occupied by the circuit is decreased, but IR-drop increases
Solution Approach 1:
The circuit segments the power distribution path into multiple parallel current paths, reducing the current density in each individual path. This segmentation lowers the I²R losses and minimizes IR-drop across the power supply network, enabling compact ASIC design without excessive voltage drop.
Solution Approach 2:
The patent merges multiple transistor devices into a unified circuit configuration where their current paths are combined in parallel between the voltage sources. This merging of parallel paths creates an equivalent lower resistance channel for current flow, reducing IR-drop while maintaining compact area.
3Area of stationary object
If the size and area footprint of ASICs is reduced, then the area occupied by the circuit is decreased, but timing performance deteriorates
Solution Approach 1:
By segmenting the current path into multiple parallel channels, the patent reduces the resistance and RC time constants in each path. This segmentation accelerates the charging and discharging of load capacitances, improving signal propagation speed and timing performance within the compact area footprint.
Data Source
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AI summary
A MOS device includes a first MOS transistor having a first MOS transistor source, a first MOS transistor drain, and a first MOS transistor gate. The MOS device also includes a second MOS transistor having a second MOS transistor source, a second MOS transistor drain, and a second MOS transistor gate. The second MOS transistor source and the first MOS transistor source are coupled to a first voltage source. The MOS device includes a third MOS transistor having a third MOS transistor gate, the third MOS transistor gate between the first MOS transistor source and the third MOS transistor source, the third MOS transistor further having a third MOS transistor source and a third MOS transistor drain, the third MOS transistor source being coupled to the first MOS transistor source, the third MOS transistor drain being coupled to the second MOS transistor source, the third MOS transistor gate floating.