Source-Side Erase Vertical NAND Strings
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently erasing data from vertical NAND strings, particularly in selectively applying erase voltages to ensure accurate data deletion without affecting unselected blocks.
Innovation Solution
The implementation of a three-dimensional memory device with a peripheral circuit that allows for erasing from the source side by applying a high erase voltage to the source line, a low voltage or 0 V to the bit lines, and differential drain-select-level voltages to selectively disconnect and reconnect vertical semiconductor channels, ensuring data erasure in a selected block while maintaining unselected blocks intact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high erase voltage is applied to the source line to erase data from vertical NAND strings, then data erasure is achieved, but unselected blocks may be accidentally erased due to voltage leakage
Solution Approach 1:
The memory device is divided into multiple independently controllable blocks with separate bit line pairs and drain-select-level electrically conductive layers for each block. This segmentation allows the erase operation to be confined to a specific selected block while unselected blocks remain isolated and unaffected by voltage leakage.
Solution Approach 2:
Different voltage levels are applied to different blocks based on their selection status. The selected block receives the high erase voltage on the source line, while unselected blocks maintain lower voltages through their respective control mechanisms. This local differentiation ensures that only the intended block undergoes erasure.
2Reliability
If differential drain-select-level voltages are applied to selectively disconnect vertical semiconductor channels, then precise erasure control is achieved, but device complexity increases
Solution Approach 1:
The drain-select-level electrically conductive layers are dynamically controlled with different voltage levels during the erase operation. By adjusting the voltage states of these conductive layers, the device can selectively connect or disconnect vertical semiconductor channels in different blocks, enabling precise control over which blocks undergo erasure without permanent structural modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise and efficient data erasure in selected memory blocks without affecting unselected blocks, improving the reliability and accuracy of data deletion in three-dimensional memory devices.
Implementation Method 1
applying a relatively high erase voltage to the source line
Implementation Method 2
applying a first drain-select-level voltage that is less than the erase voltage to one of the first drain-select-level electrically conductive layers located within the selected block, and applying a second drain-select-level voltage that is greater than the first drain-select-level voltage and not greater than the erase voltage to one of the second drain-select-level electrically conductive layers located within the selected block
Data Source
AI summary
A method of erasing vertical NAND strings from a source side of the vertical NAND strings includes applying a relatively high erase voltage to a source line, applying a relatively low voltage or 0 V to bit lines, applying a first drain-select-level voltage that is less than the erase voltage to one of the first drain-select-level electrically conductive layers, and applying a second drain-select-level voltage that is greater than the first drain-select-level voltage and not greater than the erase voltage to one of the second drain-select-level electrically conductive layers.