Source-Side Seeding for 3D NAND Memory Disturb Mitigation
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Solution Overview
Problem
In three-dimensional NAND memory arrays, the potential in the channel region is often unstable during programming operations, leading to disturb effects in unselected victim memory cells, which can alter their intended data state due to parasitic programming or high electric fields generated by neighboring cells, especially as memory storage densities increase.
Innovation Solution
Implementing source-side seeding operations concurrently with data line set operations to stabilize the channel region voltage, reducing the time required for each programming operation and minimizing disturb effects without the need for traditional drain-side seeding methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If traditional drain-side seeding operations are performed before programming operations, then the channel region voltage can be stabilized, but the programming operation time increases and additional process steps are required
Solution Approach 1:
The patent merges the seeding operation with the programming operation by simultaneously applying the programming voltage to the word line and the seeding voltage to the source line. This combination allows the channel region voltage to be stabilized during the programming process itself, eliminating the need for separate pre-seeding steps and reducing total operation time while maintaining voltage stability.
Solution Approach 2:
The patent applies the seeding voltage to the source line in advance of the actual programming pulse, preparing the channel region voltage to the appropriate level before data programming begins. This preliminary voltage establishment ensures that when programming starts, the channel is already in the optimal voltage state, preventing disturb effects without requiring extended programming time.
2Productivity
If programming operations are performed at high speed, then productivity increases, but disturb effects in unselected victim memory cells increase due to unstable channel region voltage
Solution Approach 1:
The patent introduces the source line as an intermediary element that can independently control the channel region voltage through dedicated source line voltages. This intermediary control mechanism allows the channel voltage to be stabilized during high-speed programming operations, preventing parasitic programming effects in unselected victim memory cells while maintaining overall programming speed and productivity.
3Manufacturing precision
If more programming pulses are used to ensure complete programming, then programming thoroughness improves, but the time required for each programming operation increases
Solution Approach 1:
The patent changes the voltage parameters by applying elevated source line voltages during programming operations. This parameter change ensures that the channel region maintains appropriate voltage levels throughout the programming process, enabling complete and thorough programming of all selected memory cells in a single programming pulse rather than requiring multiple incremental pulses, thereby reducing total programming duration while maintaining programming thoroughness.
Data Source
AI summary
A device might include a common source, a three-dimensional array of memory cells, a plurality of access lines, and a controller. The three-dimensional array of memory cells might include a plurality of NAND strings. Each NAND string might be selectively connected between a corresponding data line and the common source. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each NAND string of the plurality of NAND strings. The controller might be configured to access the three-dimensional array of memory cells to implement a source-side seeding operation.