Source-Synchronous Interface Calibration for Data-Clock Skew
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Solution Overview
Problem
Synchronous dynamic random access memories (SDRAMs) face challenges in robust data acquisition due to skew on the data bus and between the source clock and data bus, which is exacerbated by on-chip variation and variations in voltage and temperature, limiting effective data eye sampling and timing calibration.
Innovation Solution
A control device with a data path, clock path, multiplexing circuit, and calibration unit that adjusts delay values to maintain a relative delay between the data and clock paths, aligning signals and centering the source clock within the data eye, while compensating for on-chip process variations and voltage-temperature changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay matching is attempted during implementation of the control device, then data acquisition robustness is improved, but on-chip variation causes delay variation that undermines the matching
Solution Approach 1:
The patent implements dynamic delay adjustment through calibration units that continuously adapt delay values based on detected skew conditions. The data delay unit and clock delay unit are made dynamically adjustable rather than fixed, allowing the system to compensate for on-chip variation and voltage-temperature changes in real-time, thereby maintaining reliable data acquisition despite manufacturing variations.
Solution Approach 2:
The patent employs feedback mechanisms where the calibration unit monitors the actual delay skew between data and clock paths and adjusts the delay units accordingly. This closed-loop feedback system detects timing errors and corrects them by modifying delay values, ensuring that manufacturing precision deficiencies are compensated through continuous adjustment based on actual operating conditions.
2Measurement precision
If delay matching is designed for a particular voltage and temperature point, then timing calibration is achieved at that point, but delay variation occurs when voltage and temperature change
Solution Approach 1:
The calibration units dynamically adjust delay values in response to changing voltage and temperature conditions. Rather than being fixed at a single calibration point, the delay units can adapt their delay characteristics as operating conditions vary, maintaining timing accuracy across different voltage-temperature environments through continuous or periodic recalibration.
Solution Approach 2:
The patent changes the delay parameters of the data and clock paths based on detected operating conditions. By adjusting delay values as a variable parameter rather than a fixed design constant, the system maintains timing calibration accuracy across varying voltage and temperature conditions, effectively adapting to environmental changes.
3Measurement precision
If skew compensation techniques are implemented, then data eye sampling effectiveness is improved, but device complexity increases due to additional calibration circuits
Solution Approach 1:
The patent segments the skew compensation function into separate calibration units for the data path and clock path. Each delay unit is independently controllable and calibrated, allowing precise adjustment of each path without requiring complex interdependent circuits. This segmentation improves data eye sampling effectiveness while managing overall device complexity through modular design.
Data Source
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Figure 3
Figure 4A~4B
AI summary
In an example, a control device (104) includes a data path (322), a clock path (324), a multiplexing circuit (315), and a calibration unit (302). The data path comprises a data delay unit (310) coupled to a data input of a sampling circuit (319). The clock path comprises a clock delay unit (312) coupled to a clock input of the sampling circuit. The multiplexing circuit selectively couples a reference clock or a data bus to an input of the data delay unit, and selectively couples the reference clock or a source clock to an input of the clock delay unit. The calibration unit is coupled to a data output of the sampling circuit. The calibration unit is operable to adjust delay values of the data delay unit and the clock delay unit based on the data output of the sampling circuit to establish and maintain a relative delay between the data path and the clock path.