Source-Synchronous Circuit Timing Reconciliation for Deterministic Links
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Solution Overview
Problem
Conventional source-synchronous interconnects in ASICs are susceptible to non-determinism due to clock insertion differences between the source and responder modules, complicating system validation and at-speed testing.
Innovation Solution
A source-synchronization system that includes a source module with an asynchronous FIFO block and a responder module communicatively coupled through re-timers, where an initial determinism reconciliation signal is propagated back to the source module to compensate for intrinsic delays, effectively eliminating non-deterministic behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional source-synchronous interconnects are used to achieve high-speed data transmission, then bandwidth and speed are improved, but non-deterministic behavior occurs due to clock insertion differences between source and responder modules
Solution Approach 1:
The patent applies preliminary action by sending a determinism reconciliation signal from the source module to the responder module and back before actual data transmission begins. This preliminary signal traversal allows the system to measure and compensate for clock insertion differences in advance, establishing deterministic timing relationships before high-speed data transmission occurs, thus eliminating non-deterministic behavior while maintaining high speed
2Productivity
If source-synchronous interconnects are used to improve bandwidth, then data transmission capacity increases, but system validation and at-speed testing become complicated due to non-determinism
Solution Approach 1:
The patent implements feedback by having the responder module send the determinism reconciliation signal back to the source module after receiving it. This create a closed-loop feedback path that allows the source module to measure the round-trip timing characteristics and compensate for clock insertion differences. The feedback mechanism enables automatic calibration of timing relationships, simplifying system validation and testing while maintaining high bandwidth performance
Data Source
AI summary
Source-synchronization between a source module and a responder module generally includes providing, at the source module, an initial determinism reconciliation signal, propagating the initial determinism reconciliation signal from the source module to the responder module and back to the source module to produce a received determinism reconciliation signal, and compensating for an intrinsic delay of the circuit based on the initial determinism reconciliation signal and the received determinism reconciliation signal.