Source Synchronous Interface for Fewer Cross-Voltage Signals
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Solution Overview
Problem
In chips supporting dynamic voltage and frequency scaling (DVFS) technology, asynchronous bridge schemes used for data transfer across voltage domains result in an increased number of signals crossing voltage domains, leading to reduced efficiency due to excessive level conversions, increased area, and power consumption.
Innovation Solution
A source synchronous interface circuit is implemented with a first circuit on the master voltage domain side converting a source clock signal into a source synchronous clock signal, and a level conversion circuit adapting the data and clock signal for the slave voltage domain, while an asynchronous data storage queue is placed on the slave voltage domain side to store the data, reducing the amount of cross-voltage-domain data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asynchronous FIFO queues are used for data transmission across voltage domains, then data transfer capability is achieved, but the number of signals crossing voltage domains increases
Solution Approach 1:
The patent extracts the asynchronous FIFO queue from the cross-voltage-domain interface and places it entirely within the slave voltage domain. This removes the need for pointers and control signals to cross voltage domains, leaving only the data payload and clock signal to traverse the voltage domain boundary, thereby significantly reducing the number of cross-voltage-domain signals.
Solution Approach 2:
The patent segments the data transmission system into distinct functional blocks: the master voltage domain contains only the data source, the voltage domain boundary handles only data and clock signals, and the slave voltage domain contains the asynchronous FIFO queue. This segmentation isolates the complex FIFO operations to a single voltage domain, reducing cross-domain signal requirements.
2Loss of information
If all data and pointers are transmitted across voltage domains, then complete data information is transferred, but area consumption increases
Solution Approach 1:
The patent extracts the pointer logic and control data from the cross-voltage-domain transmission path and relocates them to the slave voltage domain where they can operate locally within the asynchronous FIFO queue. This eliminates the need for wide data buses to carry pointer information across voltage domains, thereby reducing area consumption.
3Adaptability or versatility
If multiple signals perform level conversion across voltage domains, then voltage domain compatibility is achieved, but power consumption increases
Solution Approach 1:
The patent extracts the level conversion requirement from all data and control signals and applies it only to the essential data payload and clock signal. By removing pointers and control information from the cross-voltage-domain path, the number of level conversion operations is dramatically reduced, thereby lowering power consumption.
4Adaptability or versatility
If asynchronous FIFO queues include all data and pointers, then data transmission functionality is complete, but data transmission efficiency decreases
Solution Approach 1:
The patent extracts the pointer management logic from the cross-voltage-domain interface and places it entirely within the slave voltage domain. This allows the master voltage domain to transmit data at its native clock rate without waiting for slave domain readiness, as the slave domain independently manages its FIFO queue and readiness signals, thereby improving data transmission efficiency.
Data Source
AI summary
A source synchronous interface circuit includes a first circuit, a level conversion circuit, and a second circuit. The first circuit is located on a master voltage domain side and configured to: obtain valid data and convert a source clock signal into a source synchronous clock signal corresponding to the valid data. The level conversion circuit is configured to: perform level conversion on the valid data and the source synchronous clock signal outputted by the first circuit to a slave voltage domain range of the second circuit and output the valid data and the source synchronous clock signal after level conversion to the second circuit. The second circuit is located on a slave voltage domain side and configured to: receive the valid data and the source synchronous clock signal and store the valid data into an asynchronous data storage queue based on the source synchronous clock signal.