Source-Synchronous Chip Interface for Fast Turn-On and Low Jitter
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Solution Overview
Problem
Achieving effective power reduction in mobile system link architectures is challenging due to inconsistent power consumption and latency, and architecting power modes for bandwidth agility and low total power involves additional delay and power supply transients.
Innovation Solution
The implementation of a low power, high performance source synchronous chip interface with a fast turn-on bias circuit, current mode logic (CML) clock buffers, and digitally controlled delay lines (DCDLs) to reduce power supply ringing and jitter, along with injection-locked oscillator (ILO)-based clock generation and matched source-synchronous clocking (MSSC) for phase alignment and duty-cycle correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If traditional low-power interfaces are used, then power consumption is reduced, but turn-on and clock phase lock acquisition times increase
Solution Approach 1:
The patent implements dynamic power mode switching that adapts the interface operation mode based on system requirements. The interface can transition between different power modes (including a new fast turn-on mode) to optimize both power consumption and acquisition time, making the system dynamically adjustable rather than fixed in a single low-power state
Solution Approach 2:
The patent changes key operational parameters including voltage levels, current settings, and timing characteristics to enable fast turn-on capability. By adjusting these parameters during mode transitions, the system achieves rapid acquisition without being constrained by traditional low-power interface limitations
2Use of energy by stationary object
If power modes are architected for bandwidth agility and lower total power, then power efficiency is improved, but additional delay and power supply transients occur
Solution Approach 1:
The patent prepares the interface for rapid mode transitions by pre-configuring circuit paths and maintaining certain states ready for quick switching. This preliminary preparation reduces the actual transition delay when power mode changes are required, enabling faster adaptation between bandwidth and power-saving modes
3Speed
If fast turn-on bias circuit and CML clock buffers are implemented, then turn-on speed is improved, but power supply ringing and jitter increase
Solution Approach 1:
The patent acknowledges that fast switching inherently generates power supply noise and jitter, but converts this challenge into a benefit by designing the system to operate optimally in these conditions. The source-synchronous architecture and careful timing design make the system robust to these effects, turning the fast-switching byproduct into acceptable performance characteristics
4Reliability
If source-synchronous signaling is implemented, then immunity to power supply noise is improved, but duty-cycle errors may occur
Solution Approach 1:
The patent incorporates duty-cycle correction mechanisms that monitor and adjust the clock signal characteristics. This feedback approach detects duty-cycle errors and compensates for them, maintaining signal integrity while preserving the noise immunity benefits of source-synchronous signaling
Data Source
AI summary
A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.