Source-Synchronous Chip Interface for Fast Turn-On and Low Jitter
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Solution Overview
Problem
Achieving effective power reduction in mobile system link architectures is challenging due to inconsistent power consumption and latency, and architecting power modes for bandwidth agility and low total power involves additional delay and complexity.
Innovation Solution
The implementation of a low power, high performance source synchronous chip interface with a fast turn-on bias circuit, current mode logic (CML) clock buffers, and matched source-synchronous clocking (MSSC) systems that rapidly transition between power states, reducing power supply ringing and jitter, and using distributed duty-cycle corrections to minimize power consumption and noise rejection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional power reduction techniques are used in mobile system link architectures, then power consumption is reduced, but latency increases and power consumption becomes inconsistent
Solution Approach 1:
The bias circuit is pre-charged to a predetermined voltage level before the interface circuit is activated. This preliminary action stores energy in the bias circuit's capacitive elements, enabling the interface circuit to reach full operational speed immediately upon activation without requiring a gradual ramp-up period, thereby eliminating the latency penalty typically associated with power reduction techniques.
Solution Approach 2:
The system dynamically transitions between different power states (low-power standby and full-power operation) without intermediate states. The bias circuit enables instantaneous switching by maintaining pre-charged conditions, allowing the interface to jump directly from zero power consumption to full data rate transmission, achieving both power efficiency and low latency.
2Use of energy by moving object
If power modes are architected for bandwidth agility and lower total power, then power consumption is reduced, but additional delay is introduced to change between power modes
Solution Approach 1:
The bias circuit maintains a pre-charged state during low-power modes, performing the energy preparation work in advance. When transitioning to full-power mode, the interface circuit immediately utilizes this pre-stored energy, eliminating the delay that would otherwise be required to charge the bias circuit from scratch. This enables instantaneous power mode changes without sacrificing power efficiency.
3Speed
If fast turn-on is implemented to reduce latency, then transition speed is improved, but power supply ringing and jitter increase
Solution Approach 1:
The bias circuit is designed with predetermined capacitance and voltage levels that act as a cushion against sudden current transients. By pre-charging the bias circuit to a specific voltage, the system smooths the power delivery during fast transitions, reducing ringing and jitter while maintaining rapid turn-on capability. The pre-charged bias circuit absorbs and releases energy in a controlled manner, cushioning the power supply from harsh transients.
4Use of energy by moving object
If distributed duty-cycle corrections are used to minimize power consumption, then power efficiency is improved, but circuit complexity increases
Solution Approach 1:
The duty-cycle correction function is segmented and distributed across multiple points in the clock path rather than being implemented as a single centralized correction circuit. This segmentation allows each segment to perform a portion of the correction task, achieving overall power efficiency through coordinated operation of simpler distributed elements, thereby reducing the complexity burden of any single circuit block.
Data Source
AI summary
A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.