Source-Synchronous Memory Signaling With Discontinuous Timing Calibration
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Solution Overview
Problem
Modern memory systems face significant power consumption and heat generation due to continuously clocked circuits used for timing calibration, which are necessary to compensate for voltage and temperature-dependent timing skew in source synchronous signaling.
Innovation Solution
Implementing discontinuous timing calibration in memory devices, where continuously clocked circuits are limited to the memory controller, allowing memory devices to operate without locked loops or other power-consuming timing circuitry, and using phase detection and adjustment mechanisms to maintain data sampling alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If continuously clocked circuits are used for timing calibration in memory devices, then timing skew compensation is maintained, but power consumption increases
Solution Approach 1:
The patent implements discontinuous timing calibration by periodically updating timing calibration values only during data transmission events, rather than continuously clocking calibration circuits. The memory device receives timing calibration values from the memory controller during active data operations and applies these calibrations intermittently, eliminating the need for continuous clocking while maintaining timing accuracy during data transfers.
2Measurement precision
If locked loop circuits are implemented in memory devices for timing calibration, then timing precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts the continuous timing calibration function from the memory device and relocates it to the memory controller. The memory controller generates and transmits timing calibration values to the memory device, which then applies these values using simple circuitry. This removes complex locked loop circuits from the memory device while maintaining timing precision through external calibration management.
3Measurement precision
If source synchronous signaling is used to maintain phase relationship, then data sampling alignment is improved, but signal skew from fan-out differences increases
Solution Approach 1:
The patent implements a feedback mechanism where the memory controller monitors timing relationships and generates timing calibration values based on observed skew conditions. These calibration values are transmitted back to the memory device to adjust sampling timing, creating a closed-loop system that compensates for fan-out induced skew while maintaining source synchronous signaling benefits.
Data Source
AI summary
Within a system of integrated circuit devices, first and second signals are transmitted intermittently from a first integrated circuit device to a second integrated circuit device. The second integrated circuit device generates a timing signal based on transitions of the second signal and generates samples of the first signal in response to transitions of the timing signal. The second integrated circuit device further generates timing error information based on the samples of the first signal, the timing error information to enable adjustment of the relative phases of the timing signal and the first signal.