Source Synchronous Interface Transition Fault Testing
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Solution Overview
Problem
Transition testing of source synchronous interfaces in integrated circuits is challenging due to the need for separate and independent internal tests on each side of the interface, which can be complex and time-consuming.
Innovation Solution
A method and apparatus for conducting a transition test using a source synchronous transmitter and receiver with scannable flops, exclusive OR gates, and clock gating circuits, allowing for the transmission and capture of logical transitions across the interface at operational clock speed, enabling efficient verification of transition functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate and independent internal transition tests are conducted on each side of the source synchronous interface, then transition functionality can be verified, but testing time and complexity increase
Solution Approach 1:
The patent merges the transition testing of both sides of the source synchronous interface into a single coordinated test operation. The transmitter and receiver are tested simultaneously through a unified test mechanism that applies test patterns to both sides concurrently and correlates the results, eliminating the need for separate independent tests while maintaining comprehensive transition functionality verification
Solution Approach 2:
The patent implements feedback mechanisms where test results from one side of the interface are used to control or adjust testing on the other side. The transmitter and receiver testing are coupled through feedback loops that enable coordinated test pattern application and result correlation, allowing the test system to adaptively verify transitions across the interface while reducing overall testing time
2Reliability
If separate and independent internal transition tests are conducted on each side of the source synchronous interface, then transition functionality can be verified, but test complexity increases
Solution Approach 1:
The patent combines multiple independent test operations into a single integrated test system. By merging the transmitter and receiver testing into one coordinated operation with unified control and result correlation, the patent reduces the overall test complexity while maintaining comprehensive verification of transition functionality across the source synchronous interface
Solution Approach 2:
The patent creates a universal test mechanism that can simultaneously perform multiple testing functions on both sides of the interface. The test system is designed to handle transmitter and receiver testing through a single multi-functional apparatus, reducing the need for separate specialized test setups and thereby simplifying the overall test complexity
Data Source
AI summary
A method and apparatus for conducting a transition test of a source synchronous interface is disclosed. A system includes a source synchronous transmitter and source synchronous receiver. The source synchronous transmitter includes a first scannable flop having an output coupled to a data input of a second scannable flop in the source synchronous receiver. During a transition test, the source synchronous transmitter is configured to transmit data from the first scannable flop to the second scannable flop, along with a clock signal at an operational clock speed. The first scannable flop is coupled to feedback circuitry configured to cause transitions of the transmitted data. The second scannable flop may capture the transmitted data. The captured data may be subsequently used to determine if the desired transitions were detected by the second scannable flop.