Semiconductor Contact Via Asymmetry for Lower Source Resistance
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Solution Overview
Problem
Conventional semiconductor devices face performance degradation due to increasing contact resistance as technology nodes shrink, primarily because the contact surface area on the drain side is limited, whereas the source side vias do not extend beyond the width boundaries of the source/drain contacts.
Innovation Solution
Designing source vias with a larger contact surface area compared to drain vias by extending them beyond the width boundaries of the source contacts, thereby increasing the contact surface area and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source vias are made with the same size as drain vias within the width boundaries of source/drain contacts, then manufacturing simplicity is maintained, but contact resistance increases and device performance degrades
Solution Approach 1:
The patent applies asymmetry by making source vias larger than drain vias. Specifically, source vias have a first via width while drain vias have a second via width that is smaller than the first via width. This asymmetric design increases the contact surface area on the source side, reducing contact resistance and improving device performance while accepting the resulting structural complexity.
Solution Approach 2:
The patent applies local quality by optimizing the via size specifically on the source side where larger contact area is needed to reduce contact resistance. The source vias are made larger than drain vias to address the local requirement for lower contact resistance at the source contact interface, while drain vias maintain their conventional size.
2Reliability
If source vias are extended beyond the width boundaries of source contacts, then contact surface area increases and contact resistance decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements asymmetry by defining different via widths for source and drain vias. Source vias have a first via width that extends beyond the width boundaries of source contacts, while drain vias have a smaller second via width. This asymmetric configuration increases the contact surface area on the source side, thereby reducing contact resistance despite the increased manufacturing precision requirements.
3Reliability
If contact surface area is increased on the source side, then contact resistance is reduced, but device geometry complexity increases
Solution Approach 1:
The patent applies asymmetry by creating via structures where source vias have a larger cross-sectional area than drain vias. The source vias are designed with a first via width that is greater than the second via width of drain vias, resulting in increased contact surface area on the source side. This reduces contact resistance while introducing geometric complexity to the overall device structure.
Solution Approach 2:
The patent applies local quality by enhancing the via geometry specifically on the source side where larger contact area is required. The source vias are made larger than drain vias to address the local need for reduced contact resistance at the source contact interface, while drain vias maintain their conventional smaller geometry.
Data Source
AI summary
A semiconductor device includes a source region and a drain region, a first source contact, a first drain contact, a first drain via and a first source via. The source region and the drain region are located over a substrate. The first source contact is disposed on the source region, and the first drain contact is disposed on the drain region. The first drain via is connected to the first drain contact, wherein the first drain via includes a barrier-less body portion. The first source via is connected to the first source contact, wherein the first source via includes a body portion and a barrier layer surrounding the body portion, and a size of the first source via is greater than a size of the first drain via.