Source/Drain Engineering for 10 nm FinFET Devices
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Solution Overview
Problem
The challenge in semiconductor device manufacturing lies in effectively cleaning and recessing silicon substrates for Group IV source/drain growth in FinFET devices, as existing methods fail to completely remove native oxide layers and contaminants, which negatively impact the quality of the epitaxial layer formed.
Innovation Solution
A method involving a low-pressure processing environment with a hydrogen argon gas mixture to break silicon-oxygen bonds, followed by deposition of a NH4F salt to remove contaminants, and subsequent recessing using a H2/Cl2/Ar plasma for precise etching, ensuring a clean and defect-free surface for Group IV source/drain growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional cleaning methods are used to remove native oxides and contaminants from the monocrystalline silicon surface, then some contaminants are removed, but some contaminants remain and the quality of the epitaxial layer is still negatively affected
Solution Approach 1:
The patent applies parameter changes by transitioning from conventional atmospheric pressure cleaning to low pressure plasma cleaning. This parameter change in the processing environment enables more effective removal of contaminants including carbonaceous deposits that conventional methods cannot completely eliminate, thereby improving both surface cleanliness and epitaxial layer quality
Solution Approach 2:
The patent replaces mechanical/chemical cleaning methods with plasma-based cleaning. The low pressure plasma environment generates reactive species that chemically react with and remove contaminants through volatile product formation, substituting the mechanical scraping and chemical etching of conventional methods with a more effective plasma chemistry-based cleaning mechanism
2Productivity
If the substrate is exposed to typical fabrication facility ambient conditions during processing, then the processing steps can be performed, but the substrate surface becomes susceptible to contamination and native oxide formation
Solution Approach 1:
The patent implements an inert atmosphere by maintaining low pressure plasma environment throughout the cleaning and recessing processes. This inert environment prevents oxidation and contamination of the silicon surface by excluding reactive atmospheric gases, thereby eliminating the harmful contamination effects while allowing continuous processing
Solution Approach 2:
The patent applies preliminary action by performing low pressure plasma cleaning and recessing steps immediately before epitaxial growth without exposing the substrate to atmospheric conditions. This continuous low pressure processing sequence prepares the surface in advance for high-quality epitaxial growth by removing contaminants and creating a clean, controlled surface environment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a substrate surface free of contaminants and defects, enabling precise fin size control and increased yield in sub-10 nm FinFET devices, preparing the surface for subsequent epitaxial growth while minimizing silicon-silicon lattice damage.
Implementation Method 1
establishing a low pressure processing environment in the processing volume
Implementation Method 2
delivering a first gas containing hydrogen and argon to the processing volume, the hydrogen argon gas mixture to break silicon-oxygen bonds
Implementation Method 3
deposition of a NH4F salt to remove contaminants
Implementation Method 4
subsequent recessing using a H2/Cl2/Ar plasma for precise etching
Implementation Method 5
H2/Cl2/Ar plasma for precise etching
Implementation Method 6
heating the substrate to greater than 90° C.
Data Source
AI summary
Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.