SOVA Reliability Memory Layout With Compact Stages
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Solution Overview
Problem
Soft output Viterbi algorithm (SOVA) decoders are complex and costly in terms of hardware resources due to the high number of logic units and memory required for storing reliability values, especially when dealing with convolutional encoders that have a large number of states, leading to increased chip area and power consumption.
Innovation Solution
The proposed SOVA decoder architecture includes a reliability memory unit with compact stages that have fewer logic units than full stages, with each compact stage comprising functionality equivalent to multiple full stages, reducing the overall number of logic units and memory needed, while maintaining performance by merging paths and using fewer buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional SOVA decoder architecture with full stages is used, then decoding reliability is maintained, but hardware complexity and memory resources increase significantly
Solution Approach 1:
The reliability memory unit is segmented into different types of stages (full stages and compact stages) along the decoding path. Full stages contain logic units for all states, while compact stages contain logic units for only half or less of the states. This segmentation allows the decoder to maintain reliability where needed while reducing complexity in other regions.
Solution Approach 2:
Different stages of the reliability memory unit have different qualities - full stages provide complete state coverage for higher reliability, while compact stages provide reduced state coverage for lower complexity. The system applies different levels of processing quality at different locations in the decoding path based on local requirements.
2Reliability
If traditional SOVA decoder architecture with full stages is used, then decoding performance is maintained, but memory resources and chip area increase
Solution Approach 1:
The reliability memory unit is divided into full stages and compact stages. Compact stages use fewer logic units and less memory by processing only a subset of states, thereby reducing the chip area required while maintaining overall decoding performance through the combination of different stage types.
Solution Approach 2:
Compact stages perform partial processing by handling only half or less of the states compared to full stages. This partial action is sufficient to maintain decoding performance while significantly reducing the memory and logic unit resources required, thus reducing chip area.
3Reliability
If traditional SOVA decoder architecture with full stages is used, then complete state transition evaluation is achieved, but power consumption increases
Solution Approach 1:
The reliability memory unit segments state processing across different stage types. Compact stages process fewer states with reduced logic units, thereby reducing the number of active circuit elements and associated power consumption, while full stages handle the remaining states to maintain overall evaluation accuracy.
Solution Approach 2:
Different stages apply different levels of processing quality - full stages provide complete state evaluation with higher power consumption, while compact stages provide reduced state evaluation with lower power consumption. This local differentiation optimizes the balance between power consumption and evaluation accuracy.
Data Source
AI summary
A soft output Viterbi algorithm (SOVA) decoder arranged to decode symbols received over a transmission channel, the symbols indicating a state transition between two states of a plurality of states that determines a decoded data value, the SOVA decoder comprising a reliability memory unit including at least four stages of logic units, each logic unit including a single buffer and at least four stages including a plurality of full stages comprising a separate logic unit corresponding to each of the plurality of states; and a plurality of compact stages including half or less than half the number of logic units than the number of the plurality of states, each logic unit corresponding to two of the plurality of states.