Shared SOVA Memory Reservation for LDPC Global Iteration

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Solution Overview

Problem

In error correction systems, encoded data may fail LDPC decoding due to noise, necessitating repeated Viterbi decoding for global iteration, which is inefficient without a mechanism to prioritize and manage data flow effectively.

Innovation Solution

Implementing a shared soft output Viterbi algorithm (SOVA) with a buffering mechanism that prioritizes LDPC decoder outputs for retry and utilizes ADC memory to manage data flow, allowing Viterbi decoder to process both ADC and LDPC data in a multiplexed manner, thereby optimizing processing time and reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Viterbi decoding is performed repeatedly for global iteration when LDPC decoding fails, then error correction capability is improved, but processing time increases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidprocessing time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary Viterbi decoding before LDPC decoding to generate initial soft outputs and metrics. These preliminary results are stored and can be quickly reused during global iteration when LDPC decoding fails, avoiding redundant Viterbi decoding operations and reducing processing time while maintaining error correction capability

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent merges the Viterbi decoder and LDPC decoder into a unified error correction system where soft outputs from Viterbi are shared with LDPC, and extrinsic information from LDPC is fed back to Viterbi. This integrated architecture allows efficient global iteration by sharing computational resources and data structures between the two decoders, reducing overall processing time while improving reliability

Inventive Principle:

Principle #5Merging (Combining)

2Productivity

If a shared SOVA with buffering mechanism is implemented to prioritize LDPC decoder outputs, then data flow management is improved, but device complexity increases

Engineering Contradiction:

Improvedata flow management efficiencyVSAvoiddecoder architecture complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The Viterbi decoder is designed to serve multiple functions: it performs initial decoding of ADC data, provides soft outputs to LDPC decoder, and participates in global iteration when LDPC fails. The same Viterbi engine handles both ADC data and LDPC retry data through a unified interface, reducing the need for separate processing paths and minimizing added complexity while improving productivity

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

A buffer memory structure acts as an intermediary between the Viterbi decoder and LDPC decoder, temporarily storing soft outputs and managing data flow. This buffer enables prioritization of LDPC outputs for retry without requiring complex real-time scheduling logic in the decoders themselves, achieving efficient data flow management with minimal increase in device complexity

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS8572471B2SOVA sharing during LDPC global iteration

Publication Date: 2013.10.29 SK HYNIX MEMORY SOLUTIONS AMERICA INC

AI summary

Decoding is performed on input data to obtain first decoded data using a first error correction decoder. If decoding by a second error correction decoder on the first decoded data fails, decoding is performed using an output of the second decoder and using the first decoder. A reservation request is sent from the second error correction decoder to a memory prior to completion of the decoding on the first decoded data. Space is reserved in the memory in response to receiving the reservation request from the second decoder.