Service Processor SMI Message Initiation for Host Data Transactions

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current systems lack the ability for a service processor (SP) to initiate data transactions with a host computer's BIOS without waiting for the BIOS to initiate communication, limiting the SP's autonomy in data exchange.

Innovation Solution

The SP includes a processor, non-volatile memory, and a communication interface to generate system management interface (SMI) messages, allowing it to initiate data transactions with the host computer through standardized interfaces like IPMI or USB, enabling bi-directional data exchange.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the SP waits for the BIOS to initiate data transactions, then the communication protocol remains simple and unidirectional, but the SP's autonomy and ability to initiate data exchange is limited

Engineering Contradiction:
ImproveSP's ability to initiate data transactionsVSAvoidcommunication protocol complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent inverts the traditional communication model where the BIOS initiates all transactions. Instead, the SP is empowered to initiate data transactions by generating SMI messages that interrupt the CPU and trigger BIOS responses. This inversion allows the SP to actively request data or commands while maintaining compatibility with existing BIOS architectures through standardized interrupt mechanisms.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent introduces SMI (System Management Interrupt) messages as an intermediary mechanism between the SP and BIOS. These messages serve as a standardized communication protocol that enables the SP to initiate transactions without requiring direct BIOS modifications. The SMI handler in the BIOS acts as a mediator that receives SP-initiated messages and coordinates the appropriate response, thus adding versatility while managing complexity through abstraction.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Extent of automation

If the SP can autonomously initiate data transactions, then system management capability is enhanced, but the complexity of the communication interface increases

Engineering Contradiction:
ImproveSP's autonomous data transaction capabilityVSAvoidcommunication interface complexity
Core Design Contradiction:
Extent of automationVSDevice complexity

Solution Approach 1:

The patent implements a universal communication interface based on standardized SMI messages that can handle multiple types of data transactions (data requests, commands, responses) through a single protocol. This multi-functional approach allows the SP to autonomously initiate various types of transactions without requiring separate dedicated interfaces for each function, thus enhancing automation while controlling complexity through protocol reuse.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent uses parameter-based SMI message structures where different transaction types are distinguished by message parameters rather than requiring different message formats or protocols. By changing parameters within a standardized message framework, the SP can autonomously initiate diverse transactions while the BIOS handles the complexity of interpreting and responding to different parameter combinations, thus balancing automation with interface simplicity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9529750B2Service processor (SP) initiated data transaction with bios utilizing interrupt
Publication Date: 2016.12.27 AMERICAN MEGATRENDS
  • US9529750B2 patent drawing
  • US9529750B2 patent drawing
  • US9529750B2 patent drawing

AI summary

Certain aspects direct to systems and methods to perform service processor (SP) initiated data transaction with a host computer utilizing interrupts. In certain embodiments, the system includes a SP, which includes a processor, a non-volatile memory and a communication interface. The SP generates a first system management interface (SMI) message, and sends the first SMI message to the host computer to initiate a data transaction. The OS, in response to the first SMI message, execute a SMI handler in a system management random access memory (SMRAM) area at the CPU to enter a system management mode (SMM). The SMI handler then sends the notification to the SP via the communication interface. In response to receiving the notification from the SMI handler, the SP starts performing the data transaction with the host computer.