Reconfigurable Spacecraft Processor Modules for Faster Mission Tailoring
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Solution Overview
Problem
The high cost and lengthy development time of custom-designed Application-Specific Integrated Circuits (ASICs) for spacecraft mission control processors, which are often mission-specific and inefficient in terms of resource utilization, necessitate a more efficient and cost-effective solution for configurable electronics.
Innovation Solution
A modular, configurable mission processor (CMP) system featuring reprogrammable processor modules (RPMs) with FPGAs, a configuration manager, and separate power and I/O submodules, allowing for flexible configuration and scalability to meet specific mission requirements without redesigning the core processing capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If custom-designed ASICs are used for spacecraft mission control processors, then the processing capability is optimized for specific mission requirements, but the development time and cost increase significantly
Solution Approach 1:
The system is divided into modular Reconfigurable Processor Modules (RPMs) that can be independently configured and assembled. Each RPM contains an FPGA that can be programmed with different configurations, allowing the system to be segmented into functional units that can be developed, tested, and validated separately before integration, thereby reducing overall development time while maintaining mission-specific optimization.
Solution Approach 2:
The patent employs a universal baseboard design with standardized connectors and interfaces that can accommodate different FPGA configurations. The same physical hardware platform can be reconfigured through software to perform different mission-specific functions, eliminating the need to design custom hardware for each mission while still achieving optimized processing capabilities.
2Adaptability or versatility
If custom-designed ASICs are used for spacecraft mission control processors, then the processing capability is optimized for specific mission requirements, but the development cost increases significantly
Solution Approach 1:
The universal baseboard and modular RPM design allow a single hardware platform to serve multiple mission-specific configurations. This reduces development costs by eliminating the need to design and manufacture custom ASICs for each mission, while still providing optimized processing capabilities through FPGA configuration. The same baseboard can be reused across multiple missions with different functional requirements.
Solution Approach 2:
Instead of creating expensive custom ASICs for each mission, the system uses configurable FPGAs that can be programmed with different bitstreams to replicate the functionality of custom-designed processors. This software-based copying approach allows mission-specific processing capabilities to be achieved at a fraction of the cost of hardware customization.
3Loss of time
If reconfigurable processor modules are used instead of custom ASICs, then design time and costs are reduced through module reuse, but the system complexity increases
Solution Approach 1:
The system complexity is managed through segmentation into standardized, modular components. Each RPM is a self-contained module with defined interfaces and functions, making the overall system architecture more manageable despite the reconfigurability. The segmentation allows complex functionality to be broken down into smaller, independently validated units that can be assembled through configuration rather than physical redesign.
Data Source
AI summary
A configurable mission processor (CMP) is disclosed that includes a chassis with a plurality of reprogrammable processor modules (RPMs) disposed within the chassis. Each RPM has a baseboard with at least one field programmable gate array (FPGA) and a configuration manager configured to accept a configuration file through an externally accessible signal connector, store the configuration file, and selectably program the at least one FPGA using the configuration file. The RPM includes a power submodule that accepts unregulated power through an externally accessible power connector, generates regulated power at a plurality of voltages, and provide the regulated power to the RPM. The RPM may also include an input/output submodule configured to provide a communication channel between the at least one FPGA and external devices through its own externally accessible signal connector. The CMP also includes a backplane that provides only signal and ground interconnections between the baseboards.