Spaced-One-Hot Receiver Circuit Without Delay Elements
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Solution Overview
Problem
Existing digital receive circuits for spaced-one-hot asynchronous signals over two-wire interfaces require a delay element to ensure valid data input, which limits data link speed and complicates silicon layout, making them costly and difficult to implement.
Innovation Solution
A data receive circuit utilizing a set-reset flip-flop and an exclusive-NOR to generate a timing signal without a delay element, allowing asynchronous data reception by clocking a D-flip-flop on the rising edge of the timing signal derived from the falling edge of the line signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay element is used to ensure valid data input in the flip-flop, then data reliability is improved, but data link speed deteriorates and device complexity increases
Solution Approach 1:
The patent removes the delay element from the receiver circuit entirely. Instead of adding a delay to the clock signal, the invention extracts the timing information directly from the incoming data lines themselves by using an exclusive-OR gate to detect transitions, thereby eliminating the speed limitation and complexity associated with delay elements while maintaining reliable data capture
2Reliability
If a delay element is used to ensure valid data input, then data reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the timing function from a separate delay element and integrates it into the existing circuit structures. The exclusive-OR gate combined with existing flip-flops performs the timing function that would otherwise require a dedicated delay element, thereby reducing circuit complexity and manufacturing cost while maintaining data validity
Solution Approach 2:
The patent makes the existing circuit elements serve multiple functions. The flip-flops that capture data also generate the timing signal through their combination with the exclusive-OR gate, eliminating the need for dedicated delay elements and reducing overall circuit complexity
3Reliability
If a delay element is used to ensure valid data input, then data reliability is improved, but power consumption increases
Solution Approach 1:
The patent removes the power-consuming delay element from the circuit. The timing function is instead performed by the exclusive-OR gate and existing flip-flops, which consume less power than a dedicated delay element would require, thereby reducing overall power consumption while maintaining reliable data capture
Data Source
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AI summary
A mobile device that incorporates the MIPI D-PHY specification has data lanes for carrying data between electronic modules within the device. The data lanes may incorporate a spaced-one-hot approach for asynchronously receiving a data signal over a two-wire interface. A two-wire receive interface is provided that uses an exclusive-NOR to capture a timing signal along with a set-reset flip-flop which holds the state of the data line so that a D flip-flop that is clocked on the falling edge of the timing signal received from the exclusive-NOR gate can sample the data and provide an accurate asynchronous data output.