Spacer Self-Aligned Vias for Precise Gate and Trench Contacts
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Solution Overview
Problem
Conventional fabrication processes for integrated circuits face challenges in scaling to smaller features, particularly in forming gate contacts and trench contacts, due to variability and constraints on semiconductor processes, leading to issues like opens and shorts, and complex etch selectivity requirements.
Innovation Solution
The implementation of spacer self-aligned via structures using directed self-assembly, which involves recessing gate and trench contacts relative to spacers, and utilizing a dielectric liner to enhance process window and edge placement error margin, enabling direct contact formation over active gate regions without shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then existing process infrastructure can be maintained, but manufacturing precision and reliability deteriorate due to variability at 10nm node and below
Solution Approach 1:
The spacer structure performs self-alignment to the gate contact, automatically defining the contact position and dimensions without requiring additional alignment steps. This self-service mechanism eliminates variability introduced by manual alignment processes, thereby improving both manufacturing precision and reliability at scaled nodes
Solution Approach 2:
The spacer is formed in advance before the gate contact etching process. This preliminary action pre-defines the contact boundaries and alignment references, ensuring that subsequent etching operations achieve precise contact formation without variability, thus improving both precision and reliability
2Ease of manufacture
If complex etch processes are used to form gate contacts, then contact formation can be achieved, but device complexity and process constraints increase
Solution Approach 1:
The spacer acts as an intermediary structure that simplifies the gate contact formation process. Instead of using complex selective etching to directly define contacts, the spacer serves as a intermediate alignment reference that guides simpler etching operations, reducing etch process complexity while maintaining ease of manufacture
Solution Approach 2:
The contact formation process is segmented into distinct steps: first forming the spacer structure, then using it to guide contact etching. This segmentation breaks down the complex single-step etch process into simpler, more controllable stages, reducing overall process complexity while improving manufacturability
3Productivity
If standard cell layout is used without spacer self-alignment, then layout density can be maintained, but manufacturing yield decreases due to reduced edge placement error margin
Solution Approach 1:
The spacer structure provides self-alignment that automatically compensates for edge placement errors. By serving as its own alignment reference, the spacer increases the effective error margin, allowing higher manufacturing yield without sacrificing precision, thus resolving the contradiction between productivity and manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates the fabrication of integrated circuits with reduced standard cell area and improved manufacturing yield by allowing precise contact formation with increased edge placement error margin, eliminating the need for complex etch processes and reducing layout waste.
Implementation Method 1
a dielectric liner is over the plurality of gate structures, over the plurality of conductive trench contact structures, and over the plurality of dielectric spacers
Implementation Method 2
spacer self-aligned via structures using directed self assembly
Data Source
AI summary
Spacer self-aligned via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers protrudes above the plurality of gate structures and above the plurality of conductive trench contact structures. Individual ones of the plurality of dielectric spacers have an upper spacer portion on a lower spacer portion, with an interface between the upper spacer portion and the lower spacer portion.