Spacer Chip Groove Patterns for Semiconductor Package Reliability
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Solution Overview
Problem
There is a need for semiconductor packages that can efficiently arrange semiconductor chips in a limited space while maintaining reliability, particularly in portable electronic devices where miniaturization and weight reduction are essential.
Innovation Solution
A semiconductor package design that includes a package substrate with a lower semiconductor chip, a spacer chip with a groove pattern on its upper surface, and an upper semiconductor chip bonded using a non-conductive adhesive layer, which is surrounded by a molded portion acting as an encapsulating passivation layer, effectively utilizing space and enhancing bonding strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor chips are stacked vertically to reduce package size, then space utilization is improved, but reliability may deteriorate due to increased complexity and potential failure points
Solution Approach 1:
The package is segmented into multiple functional layers: active semiconductor chips, non-functional spacer chips with groove patterns, adhesive layers, and molded portions. This segmentation allows the spacer chips to provide structural support and protection without adding functional complexity, thereby maintaining reliability while enabling vertical stacking for compact size.
Solution Approach 2:
Spacer chips act as intermediary elements between the active semiconductor chips and the package substrate. These non-functional chips with groove patterns provide a protective interface that prevents resin flow damage and enhances bonding, serving as a mediator that protects the active components while enabling the stacked configuration.
2Ease of manufacture
If a flat bonding interface is used between chips, then manufacturing is simpler, but bonding strength is reduced
Solution Approach 1:
The bonding interface is transformed from a flat surface to a non-flat surface with groove patterns. These grooves create increased surface area and mechanical interlocking features, enhancing bonding strength between the spacer chips and adhesive layers while remaining compatible with standard manufacturing processes.
3Reliability
If resin is used to fill spaces between chips, then packaging is more complete, but resin flow may cause damage to the chips
Solution Approach 1:
The groove patterns on the spacer chips are designed to preemptively counteract resin flow before it can reach and damage the active semiconductor chips. The grooves act as barriers that redirect or contain the resin, preventing harmful flow while still allowing complete packaging of the space between chips.
Data Source
AI summary
A packaged integrated circuit device includes a substrate having a spacer chip thereon, which is devoid of active integrated circuits therein but which has a stress-relieving pattern of grooves in an upper surface thereof. A first semiconductor chip is provided, which is bonded to the upper surface of the spacer chip. A molded region is provided, which includes a passivating resin that: (i) at least partially surrounds the first semiconductor chip and the spacer chip, and (ii) extends into at least a portion of the grooves within the upper surface of the spacer chip.