Spacer on Conductive Layer Sidewall for Semiconductor Interconnect Overlay
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Solution Overview
Problem
Increasing the height of capacitor structures in semiconductor devices complicates contact formation in peripheral circuits, leading to overlay shifts and potential damage during etching, which reduces the reliability of semiconductor devices.
Innovation Solution
An interconnect structure comprising a conductive layer, a spacer on the sidewall of the conductive layer, and a dielectric layer, where the contact is formed within the dielectric layer, effectively increasing the overlay window without enlarging the device size, thereby preventing damage from overlay shifts during etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the height of the capacitor structure is increased to increase capacitance, then the capacitance is improved, but the depth of the contact opening increases making the contact process more difficult and reducing reliability
Solution Approach 1:
The patent introduces a spacer structure that extends laterally from the sidewall of the conductive layer, adding a horizontal dimension to the contact formation process. This allows the contact opening to be defined by both the conductive layer pattern and the spacer, creating a two-dimensional alignment system that compensates for overlay shifts and prevents contact opening misalignment.
2Manufacturing precision
If etching time is increased to ensure sufficient exposure of the conductive layer, then the contact opening exposure is improved, but overlay shift causes the contact opening to exceed the conductive layer range, etching adjacent dielectric layer and damaging circuit devices
Solution Approach 1:
The spacer acts as an intermediary structure between the conductive layer and the contact opening. It provides a protective boundary that defines the etching stop point, preventing the etch from damaging adjacent dielectric layers and circuit devices while ensuring sufficient exposure of the conductive layer.
Solution Approach 2:
The spacer structure is formed beforehand to create a protective cushion or buffer zone around the conductive layer. This pre-formed structure absorbs or prevents the harmful effects of over-etching, protecting adjacent sensitive structures from damage while ensuring adequate contact opening formation.
3Reliability
If the size of the conductive layer is increased to solve overlay shift, then the overlay window is improved, but the chip size is increased
Solution Approach 1:
Instead of increasing the conductive layer size in the planar dimension, the patent utilizes the vertical sidewall dimension by forming a spacer that extends laterally. This creates an additional alignment reference in the horizontal direction without increasing the footprint of the conductive layer itself, thereby improving the overlay window without increasing chip size.
Data Source
AI summary
An interconnect structure including a conductive layer, a spacer, a dielectric layer, and a contact is provided. The conductive layer is disposed on a substrate. The spacer is disposed on a sidewall of the conductive layer. The dielectric layer covers the conductive layer and the spacer. The contact is disposed in the dielectric layer and located on the conductive layer.