Spacer-Defined Double Patterning for Sub-32 nm Line Width Reduction
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Solution Overview
Problem
The existing spacer-defined double patterning process in semiconductor fabrication is limited by the minimum line width achievable, which cannot meet the requirements for high integration density and miniaturization due to constraints from light source wavelength and photoresist thickness, especially below 32 nm.
Innovation Solution
A method involving the deposition of a silicon nitride film with controlled thickness, followed by anisotropic dry etching to form spacers, and subsequent planarization and etching using a silicon dioxide film as a mask to convert spacers into trenches, allowing for precise control and reduction of minimum line width in the trench structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the existing immersion scanner with 193-nm wavelength is used for lithography, then the process can be maintained with current equipment, but the minimum line width cannot be reduced below 32 nm
Solution Approach 1:
The patent applies segmentation by dividing the single lithography exposure into multiple steps: first forming initial patterns, then using spacer deposition to create additional patterns between the original lines. This multi-step approach effectively segments the pattern formation process, enabling sub-32 nm resolution while using existing 193-nm lithography equipment.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional spacer-based patterning. By depositing spacers vertically on the sidewalls of initial patterns and then performing anisotropic etching, the process exploits the third dimension (vertical height) to define horizontal feature sizes, achieving resolution beyond the diffraction limit of the 193-nm light source.
2Manufacturing precision
If the spacer-defined double patterning process is used to reduce line width, then sub-32 nm dimensions can be achieved, but the process complexity increases
Solution Approach 1:
The patent changes key process parameters including spacer material composition (silicon nitride), deposition thickness (controlling final line width), and etching selectivity. By adjusting the spacer thickness and etching conditions, precise control over final line width is achieved while managing process complexity through parameter optimization rather than adding more process steps.
3Ease of manufacture
If the minimum line width is determined by lithography process, then the process is simple, but the minimum trench width is limited by light source wavelength and photoresist thickness
Solution Approach 1:
The patent introduces spacers as intermediary structures that mediate between the lithography-defined initial patterns and the final trench structures. The spacers act as self-aligned masks during anisotropic etching, transferring the pattern information while enabling sub-lithographic resolution. This intermediary approach maintains process simplicity by using self-aligned steps rather than requiring multiple lithography exposures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the achievement of smaller line widths, potentially below 20 nm, by determining the trench width through the thickness of the silicon nitride film, simplifying the process and enhancing control over the pattern definition in semiconductor fabrication.
Implementation Method 1
depositing a layer of silicon nitride film 106 on the interlayer dielectric layer 103 and the retention structures 104a, 104b of the sacrificial hard mask layer
Implementation Method 2
etching the silicon nitride film 106 with a dry etching process to form silicon nitride spacers 106a, 106b, 106c and 106d on both sides of the retention structures 104a, 104b
Implementation Method 3
depositing a layer of silicon dioxide film 107 on the interlayer dielectric layer 103 including the silicon nitride spacers 106a, 106b, 106c and 106d
Implementation Method 4
performing a planarization process on the silicon dioxide film 107 such that the height of the silicon dioxide film 107 around the silicon nitride spacers 106a, 106b, 106c and 106d corresponds to the heights of the silicon nitride spacers 106a, 106b, 106c and 106d
Implementation Method 5
removing the silicon nitride spacers 106a, 106b, 106c and 106d to form trenches 107a, 107b, 107c and 107d
Implementation Method 6
etching the interlayer dielectric layer 103 through the trenches 107a, 107b, 107c and 107d by using the silicon dioxide film 107 as a mask to form desired trenches 103a, 103b, 103c and 103d
Data Source
AI summary
The invention discloses a method for reducing a minimum line width in a spacer-defined double patterning process of the present invention. In the method, the silicon nitride spacers can be converted into trenches in the interlayer dielectric layer by using a silicon dioxide film as a mask and by means of a chemically mechanical polishing process and an etching process, so that the minimum line width of the trenches can be determined by the width of the silicon nitride spacers, and thus a smaller line width can be achieved and the process can be simple and easy to control.