Spacer-Die Chip-on-Wafer Packaging for Fine-Pitch HBM Signals
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Solution Overview
Problem
The manufacturing of packaging substrates for semiconductor devices is costly, and the process of attaching semiconductor dies to these substrates can lead to die warpage, which is a yield detractor, while integrated fan-out package-on-package structures face challenges in meeting fine pitch requirements for high-speed signal transmission and are not suitable for high-bandwidth memory dies.
Innovation Solution
A chip-on-wafer method combines redistribution structures with wafer-level packaging, using spacer dies to provide a low-cost structure that enables high-bandwidth high-speed signal transmission by substituting packaging substrates, allowing direct mounting of fan-out packages on printed circuit boards, and incorporating spacer dies to surround semiconductor dies for sufficient bonding pad area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If packaging substrates are used to attach semiconductor dies, then the dies can be bonded to the substrate, but the manufacturing cost increases and die warpage occurs reducing yield
Solution Approach 1:
The patent removes the packaging substrate from the assembly by directly bonding the fan-out package to the printed circuit board. The spacer die serves as a structural element that provides necessary spacing and support without requiring a separate packaging substrate, thereby eliminating the associated manufacturing costs and potential die warpage issues.
Solution Approach 2:
The spacer die performs multiple functions: it provides mechanical spacing between components, supports the bonding pad area, and enables direct mounting to the printed circuit board. This multi-functionality replaces the traditional packaging substrate, reducing manufacturing complexity and cost while maintaining bonding reliability.
2Productivity
If integrated fan-out package-on-package structures are used, then packaging density is improved, but fine pitch requirements for high-speed signal transmission cannot be met
Solution Approach 1:
The patent segments the assembly into distinct functional components: the semiconductor die, the spacer die, and the printed circuit board. This segmentation allows the semiconductor die to be optimally configured for high-speed signal transmission with appropriate bonding pad spacing, while the spacer die provides structural support, thereby achieving both packaging efficiency and fine pitch signal transmission requirements.
3Ease of manufacture
If traditional packaging methods are used, then manufacturing process is established, but high-bandwidth memory dies cannot be accommodated
Solution Approach 1:
The patent changes the structural parameters of the assembly by eliminating the packaging substrate and using the spacer die as a structural element. This parameter change enables the direct mounting configuration that is compatible with high-bandwidth memory dies, while the bonding process remains based on established manufacturing techniques, thus achieving both process maturity and adaptability.
Data Source
AI summary
A semiconductor structure may include an interposer including on-interposer bump structures, at least one semiconductor die bonded to a first subset of the on-interposer bump structures through first solder material portions, at least one spacer die bonded to a second subset of the on-interposer bump structures through second solder material portions, and a molding compound die frame laterally surrounding each of the at least one semiconductor die and the at least one spacer die. Each of the at least one semiconductor die includes a respective set of transistors and a respective set of metal interconnect structures. Each of the at least one spacer die is free from any transistor therein.