Spacer-on-Spacer Die Stack Assembly for Solder Joint Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Solder joint reliability in semiconductor devices is compromised by thermo-mechanical stress due to CTE mismatch between semiconductor packages and printed circuit boards, leading to potential disconnection, delamination, and cracking during temperature cycling.
Innovation Solution
Employing a spacer-on-spacer configuration with inert top and base spacers between the die stack and substrate, which uplifts the die to prevent direct contact and reduce stress, using materials like silicon, and applying molding compound as a buffer layer to isolate CTE effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor dies are mounted directly on substrate in grid pattern, then manufacturing density is improved, but solder joint reliability deteriorates due to thermo-mechanical stress
Solution Approach 1:
The patent introduces spacers as intermediary elements between the semiconductor die and substrate. These spacers act as mediators that decouple the direct thermal and mechanical stress pathways, allowing high-density mounting while protecting solder joints from thermo-mechanical fatigue during temperature cycling.
2Ease of manufacture
If die corner contacts substrate during wire bonding, then manufacturing process is simplified, but die stress increases leading to cracking
Solution Approach 1:
The spacers are installed beforehand to provide cushioning support under the die corners during wire bonding operations. This pre-positioned cushioning prevents direct contact between die corners and substrate, eliminating stress concentration points that would lead to cracking while maintaining process simplicity.
3Adaptability or versatility
If CTE mismatch between package and PCB is present, then material selection is easier, but solder joint reliability deteriorates during temperature cycling
Solution Approach 1:
The patent extracts the stress-coupling pathway by introducing spacers that physically separate the die stack from the substrate. This extraction breaks the direct transmission path of thermo-mechanical stress caused by CTE mismatch, allowing material selection flexibility while protecting solder joints during temperature cycling operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly enhances solder joint reliability by over 400%, reducing stress and preventing cracking, while maintaining low costs and process integrity.
Implementation Method 1
Employing a spacer-on-spacer configuration with inert top and base spacers between the die stack and substrate, which uplifts the die to prevent direct contact and reduce stress
Implementation Method 2
applying molding compound as a buffer layer to isolate CTE effects
Data Source
AI summary
A semiconductor package assembly includes a substrate, a die stack including at least a bottom die, an inert top spacer, and at least a first inert base spacer. The inert top and base spacers are exclusive of any circuits. A top surface of the inert top spacer is directly attached to a bottom surface of the bottom die in the die stack. A top surface of the first inert base spacer is directly attached to a bottom surface of the inert top spacer and a bottom surface of the first inert base spacer is directly attached to the substrate. The footprint of the inert base spacer is smaller than the footprint of the inert top spacer. In some embodiments, the footprint of the inert base spacer is positioned entirely within the footprint of the inert top spacer.