Spacer-Defined Double Patterning for Flexible Interconnect Layouts
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Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in achieving design flexibility for gate patterns using lithography-etch double patterning, particularly in forming precise interconnects with ultra-low-k dielectric films, due to limitations in existing spacer-defined processes.
Innovation Solution
The method involves a multi-phase process including first and second lithography exposures and etches, forming mandrels and spacers, and filling regions with specific materials to create trench patterns, allowing for orthogonal patterns on different layers, enhancing design flexibility and precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional lithography-etch double patterning is used, then manufacturing process is simpler, but design flexibility for gate patterns is limited
Solution Approach 1:
The fabrication process is divided into distinct phases: first lithography exposure forming mandrels, spacer formation on mandrel sidewalls, selective etching, and second lithography exposure. This segmentation allows independent optimization of each step to achieve complex orthogonal patterns while maintaining process control
Solution Approach 2:
The invention introduces vertical dimension through spacer formation on mandrel sidewalls, enabling patterns in multiple dimensions. The spacers extend vertically from the mandrels, allowing creation of three-dimensional interconnect structures and orthogonal patterns that cannot be achieved with planar lithography alone
2Manufacturing precision
If precise interconnects with ultra-low-k dielectric films are formed, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
Mandrels serve as intermediary structures that define the initial pattern, and spacers serve as intermediaries that transfer and refine the pattern to the ultra-low-k dielectric film. These intermediary structures enable precise pattern transfer while protecting the sensitive dielectric material during processing
Solution Approach 2:
The mandrels are formed in advance before the actual interconnect patterning. This preliminary action establishes a template that guides subsequent spacer formation and material deposition, ensuring precise alignment and positioning of the ultra-low-k dielectric features before the final pattern is created
3Adaptability or versatility
If spacer-defined process is used, then design flexibility is enhanced, but process steps increase
Solution Approach 1:
Multiple pattern formation operations are merged into a unified spacer-defined process flow. The mandrel formation, spacer deposition, selective removal, and second lithography exposure are combined into an integrated process that achieves orthogonal patterning in a systematic manner, improving throughput compared to separate patterning operations
Data Source
AI summary
One or more embodiments described herein include systems, and/or methods that facilitate fabrication of a semiconductor device using a spacer lithography-etch process. According to an embodiment, a method can comprise performing a first lithography exposure and etch over a first layer of a semiconductor device, where the first lithography exposure and etch comprises forming one or more mandrels on a first region of a second layer by employing a first photoresist layer. The method can further comprise forming one or more spacers on a sidewall of the one or more mandrels and covering a second region of the second layer, where the second region is adjacent to the one or more mandrels. The method can further comprise forming a cut over a third region of the second layer and filling the third region with first material.