Spacer Etch Mask for Sub-40 nm Semiconductor Pattern Formation
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Solution Overview
Problem
Current semiconductor manufacturing techniques struggle to form fine patterns below 40 nm using existing exposure apparatuses, as conventional lithography and hard mask methods face limitations due to optical and chemical effects, and pattern collapse issues.
Innovation Solution
A method involving the formation of a laminated hard mask layer with an amorphous carbon and SiON/SiN layer, a sacrificial oxide layer, and spacers is used, where spacers act as etching masks to control pattern size, allowing for fine pattern formation independent of exposure apparatus resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography with ArF exposure is used, then photoresist pattern can be formed, but fine pattern formation below 40 nm is limited due to optical and chemical effects
Solution Approach 1:
The patent introduces a spacer layer as an intermediary element between the photoresist pattern and the final etched pattern. The spacer is formed by depositing material on the sidewalls of the photoresist pattern, then selectively removing the photoresist. This intermediary spacer structure enables precise pattern transfer at dimensions below 40 nm that cannot be achieved directly through conventional lithography, resolving the contradiction between manufacturing precision and reliability.
Solution Approach 2:
The patent performs preliminary actions by forming the spacer layer on the photoresist sidewalls before the actual pattern etching. This preliminary spacer formation allows the subsequent etching process to achieve fine patterns below 40 nm with high precision and reliability, overcoming the limitations of direct conventional lithography.
2Manufacturing precision
If hard mask method is used, then etching mask can be formed, but pattern collapse occurs in semiconductor devices with feature size less than 40 nm
Solution Approach 1:
The patent uses the photoresist pattern as a temporary intermediary structure to form the spacer, then removes the photoresist. The spacer becomes the new intermediary for the etching process. This approach avoids the pattern collapse issue of hard masks at sub-40 nm dimensions while maintaining the ability to form precise patterns through the spacer-mediated etching process.
Solution Approach 2:
The patent changes the material parameter from traditional hard mask materials (nitride, amorphous carbon) to a spacer material deposited conformally on the photoresist sidewalls. This parameter change in material selection and formation method enables stable pattern structures at sub-40 nm dimensions while maintaining manufacturing precision.
3Productivity
If feature size is reduced below 40 nm, then higher integration is achieved, but existing exposure apparatuses cannot form the required fine patterns
Solution Approach 1:
The patent replaces the optical-based lithography system with a spacer-based self-aligned etching process. Instead of relying on the resolution limits of optical exposure apparatuses, the method uses conformal material deposition and selective removal to define patterns. This substitution enables existing exposure apparatuses to effectively produce sub-40 nm patterns, increasing integration density without requiring new equipment.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional spacer formation on sidewalls. By utilizing the vertical dimension for spacer deposition and then using the spacer's sidewall as the pattern definition, the method achieves sub-40 nm lateral dimensions using existing optical tools, thereby increasing productivity through higher integration without sacrificing manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of fine patterns in semiconductor devices with feature sizes less than 40 nm using existing equipment, reducing costs by avoiding the need for new exposure apparatuses and ensuring reliable, high integration of semiconductor devices.
Implementation Method 1
forming a laminated hard mask layer with an amorphous carbon and SiON/SiN layer
Implementation Method 2
A sacrificial oxide layer is formed over the hard mask layer
Implementation Method 3
forming spacers on sidewalls of the sacrificial layer pattern
Data Source
AI summary
A process for manufacturing a semiconductor device using a spacer as an etch mask for forming a fine pattern is described. The process includes forming a hard mask layer over a target layer that is desired to be etched. A sacrificial layer pattern is subsequently formed over the hard mask layer. Spacers are formed on the sidewalls of the sacrificial layer pattern. The protective layer is formed on the hard mask layer portions between the sacrificial patterns formed with the spacer. The sacrificial layer pattern and the protective layer are then later removed, respectively. The hard mask layer is etched using the spacer as an etching mask. After etching, the spacer is removed. Finally, the target layer is etched using the etched hard mask as an etching mask.