Spacer Filler Etch for Uniform Semiconductor Pattern Transfer
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Solution Overview
Problem
The increasing density of semiconductor devices leads to a critical dimension approaching the optical-physical limit of photolithography, causing over-etching in the patterning step of the capacitor process, resulting in ineffective pattern transfer and defects due to the etch loading effect between adjacent pattern structures.
Innovation Solution
A method involving the formation of a sacrificial layer with a first and second sacrificial dielectric layer, patterning to create intermediate pattern structures with gaps, forming a spacer pad layer that covers sidewalls and the bottom of the gaps, and removing the sacrificial layers to prevent over-etching and ensure uniform pattern transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the critical dimension is reduced to increase device density, then device density is improved, but over-etching occurs in the patterning step
Solution Approach 1:
The patent applies preliminary action by forming a spacer pad layer at the bottom of gaps between pattern structures before the etching process. This pre-deposited layer serves as a protective cushion that prevents over-etching from reaching the substrate, thereby enabling smaller critical dimensions without sacrificing pattern transfer accuracy.
Solution Approach 2:
The spacer pad layer acts as a beforehand cushioning layer that absorbs the excessive etching action. By positioning this protective layer at the gap bottoms prior to etching, the patent prevents the etch process from penetrating too deeply and causing defects, thus resolving the contradiction between reduced critical dimension and maintained manufacturing precision.
2Manufacturing precision
If the etching process is extended to fully transfer the pattern, then pattern transfer completeness is improved, but over-etching causes bridging or non-open defects
Solution Approach 1:
The spacer pad layer provides beforehand cushioning by being deposited at the gap bottoms before etching. This layer absorbs the excessive etching action, allowing the etch process to run long enough to fully transfer the pattern while preventing it from penetrating so deeply as to cause bridging or non-open defects.
Solution Approach 2:
The spacer pad layer serves as an intermediary element between the etching process and the substrate. It mediates the interaction by providing a protective barrier that allows complete pattern transfer while preventing the harmful effects of over-etching, thus resolving the contradiction between transfer completeness and defect rate.
3Quantity of substance
If the gap between adjacent pattern structures is reduced to increase density, then device density is improved, but etch loading effect increases causing uniformity loss
Solution Approach 1:
The patent applies local quality by depositing the spacer pad layer specifically at the bottom regions of the gaps between pattern structures, rather than uniformly throughout. This localized deposition provides targeted protection where the etch loading effect is most pronounced, maintaining pattern uniformity while allowing reduced gap dimensions for increased density.
Solution Approach 2:
By preliminarily forming the spacer pad layer at the gap bottoms before the etching process, the patent prepares protective structures in advance at the critical locations. This preliminary action compensates for the increased etch loading effect that occurs when gaps are reduced, thereby maintaining pattern uniformity at higher device densities.
Data Source
AI summary
A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed. The method of manufacturing a semiconductor structure includes: providing a substrate, and forming a first sacrificial layer on the substrate, where the first sacrificial layer includes a first sacrificial dielectric layer and a second sacrificial dielectric layer; patterning the first sacrificial layer, and forming first intermediate pattern structures that are arranged at intervals, where a first gap is provided between two adjacent first intermediate pattern structures; forming a first spacer pad layer in the first gap, where the first spacer pad layer covers sidewalls of each of the two adjacent first intermediate pattern structures and a bottom of the first gap; removing the first spacer pad layer at the bottom of the first gap, and the second sacrificial dielectric layer; and removing the first sacrificial dielectric layer, to form first pattern structures.