Spacer-Shaped Floating Gate for High-Density Flash Memory
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Solution Overview
Problem
The existing semiconductor memory devices face challenges in miniaturization due to the large size of the floating gate structure, which restricts device density, particularly in silicon storage technology flash non-volatile memory cells, as the conventional LOCOS process results in a plate-shaped floating gate that is larger than necessary.
Innovation Solution
The semiconductor memory device employs a spacer-shaped floating gate structure formed without using the LOCOS process, comprising a nitride pattern, spacer-shaped polysilicon floating gate, dielectric layer, and control gate, fabricated through specific etching and deposition processes to minimize cell size and improve device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the conventional LOCOS process is used to form the floating gate, then the floating gate can be formed with a plate shape, but the cell size becomes large which restricts device density
Solution Approach 1:
The floating gate is transformed from a two-dimensional plate shape to a three-dimensional spacer shape formed at the side walls of the nitride pattern. This dimensional change allows the floating gate to be positioned vertically along the side walls rather than extending horizontally, significantly reducing the cell area while maintaining functionality
Solution Approach 2:
The gate structure is segmented into distinct components: the nitride pattern serves as a template, the floating gate is formed as spacers at the side walls, and the control gate is positioned separately above. This segmentation allows each component to be optimized independently and reduces the overall cell footprint compared to the conventional integrated plate shape
2Reliability
If the LOCOS process including oxidation and annealing is used, then the floating gate can be formed, but the fabrication process becomes complex and time-consuming
Solution Approach 1:
The complex oxidation and annealing steps of the LOCOS process are extracted and replaced with a simpler spacer formation process. The floating gate is formed by depositing material and etching to create spacers at the side walls of the nitride pattern, eliminating the need for thermal oxidation and annealing while maintaining reliable floating gate formation
Solution Approach 2:
The thermal field-based LOCOS process (oxidation and annealing) is replaced with a mechanical/chemical etching process. The spacer-shaped floating gate is formed through controlled etching of deposited material, substituting thermal processing with a more controllable and simpler mechanical removal process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes the size of the memory cell, enhances device density, and simplifies the fabrication process by excluding the LOCOS process, thereby improving production yield and efficiency.
Implementation Method 1
forming a nitride pattern on a semiconductor substrate
Implementation Method 2
etching the polysilicon layer, the third oxide layer and the first oxide layer to form a control gate over the floating gate
Implementation Method 3
forming a dielectric layer in a spacer shape at the side wall of the floating gate
Implementation Method 4
forming a first oxide layer at the side walls of the floating gate; forming a third oxide layer over the first oxide layer
Data Source
AI summary
A semiconductor memory device is provided including: a spacer shaped floating gate formed on a semiconductor substrate; a dielectric layer spacer formed at one side wall of the floating gate; a third oxide layer formed over the floating gate and the dielectric layer; and a control gate formed over the third oxide layer. According to an embodiment, the structure of the floating gate in a plate shape whose center is concave is improved to the spacer structure, making it possible to minimize the size of the semiconductor memory device and to improve density. Moreover, a LOCOS process can be excluded while forming the floating gate, making it possible to more efficiently fabricate the device.