Spacer-Based Hard Mask Patterning for Short-Free Interconnect Spacing
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Solution Overview
Problem
Conventional self-aligned patterning processes in semiconductor fabrication often result in defects during line separation, leading to undesirable short circuits between interconnection lines due to inadequate spacing reduction.
Innovation Solution
A method involving the formation of mandrel lines, spacers, and multiple photomask etching processes to create precise linear openings in a hard mask layer, allowing for the reduction of intervals between metal patterns to achieve finer spacing and prevent short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional cut-off process is used for line separation in self-aligned patterning, then manufacturing process is simple, but defects occur causing short circuits between interconnection lines
Solution Approach 1:
The patent divides the single cut-off process into multiple sequential etching steps (first etching, second etching, third etching) with different etching conditions and selectivities. Each step targets specific regions with different requirements, segmenting the overall patterning process to achieve both fine spacing and reliable line separation without short circuits
Solution Approach 2:
The patent applies different etching selectivities and conditions to different regions of the pattern. The first etching uses high selectivity for mandrel lines, the second etching uses moderate selectivity for intermediate structures, and the third etching uses low selectivity for final interconnection lines. This local optimization ensures each region receives appropriate processing to prevent defects
2Manufacturing precision
If interval between metal patterns is reduced to achieve finer spacing, then resolution is improved, but risk of short circuits increases
Solution Approach 1:
The patent performs preliminary etching steps that create intermediate structures and partial openings before the final etching. The first and second etching steps prepare the structure by removing mandrel lines and creating intermediate patterns, which then guide the third etching to achieve precise final spacing with built-in protection against short circuits
Solution Approach 2:
The patent introduces intermediate structures (partial openings, intermediate patterns) that act as mediators between the initial mandrel lines and the final interconnection lines. These intermediate structures serve as self-aligned masks and guides, ensuring precise spacing control while preventing direct contact between adjacent interconnection lines
3Manufacturing precision
If multiple photomask etching processes are used to create precise linear openings, then manufacturing precision is improved, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple etching operations into a unified multi-step process that uses the same hard mask layer and self-aligned structures throughout. The first, second, and third etching steps are integrated using sequentially formed photomasks, merging what could be separate processes into a coordinated sequence that maintains precision while managing complexity
Data Source
AI summary
A method of fabricating a semiconductor device, includes forming a dielectric layer on a substrate; forming a hard mask layer on the dielectric layer; forming mandrel lines on the hard mask layer, each of the mandrel lines extending in a first direction; forming spacers on both sidewalls of each of mandrel lines; removing the plurality of mandrel lines from the spacers; forming a first linear opening corresponding to a first region of a space between adjacent ones of the spacers, in the hard mask layer; forming a second linear opening corresponding to a second region of the space between the adjacent ones, the second linear opening being adjacent to the first linear opening in the first direction; forming trenches in the dielectric layer using the hard mask layer; and interconnection lines by filling the trenches with a conductive material.