Spacer-Based Hole Patterning for Hexagonal Close-Packed Pitch Shrink

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Solution Overview

Problem

Existing methods for forming hexagonal close-packed hole patterns in semiconductor devices face challenges such as a large number of processes, time-consuming pattern alignment, and increased manufacturing costs due to the need for high-precision lithography and multiple side wall processing steps.

Innovation Solution

A method involving the formation of hard mask layers and spacer patterns to achieve a hexagonal close-packed arrangement of hole patterns, where the pitch is reduced by forming additional hole patterns at the center points of equilateral triangles formed by the initial hole patterns, allowing for finer patterns to be formed within a single lithography process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If cross point processing is used to form hexagonal close-packed arrangement at pitch finer than lithography limit resolution, then finer patterns can be formed, but the number of processes increases and pattern alignment becomes time-consuming

Engineering Contradiction:
Improvepattern pitchVSAvoidnumber of processes
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent divides the pattern formation into multiple stages: first forming a preliminary pattern at lithography limit resolution, then using spacer formation to create additional patterns at 1/√3 pitch. This segmentation allows achieving finer final patterns while reducing the number of lithography processes needed compared to traditional cross-point processing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary pattern formation using lithography to create the initial hole pattern, then uses this preliminary pattern as a basis for subsequent spacer-based pattern multiplication. This preliminary action eliminates the need for multiple independent lithography alignment processes, reducing both process count and alignment time.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If cross point processing is used to form hexagonal close-packed arrangement, then finer patterns can be formed, but time and effort for pattern alignment increases

Engineering Contradiction:
Improvepattern pitchVSAvoidpattern alignment time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent employs self-aligned spacer formation where the spacer patterns automatically form at precise positions relative to the preliminary hole patterns without requiring additional alignment steps. The spacer material conformally deposits on the preliminary pattern sidewalls, and subsequent anisotropic etching self-aligns the final pattern positions, eliminating manual or complex automated alignment procedures.

Inventive Principle:
Principle #25Self-service

3Manufacturing precision

If high-precision lithography and multiple side wall processing steps are used, then hexagonal close-packed arrangement can be formed, but manufacturing costs increase

Engineering Contradiction:
Improvepattern arrangementVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent changes the pitch parameter from the lithography limit resolution to 1/√3 times that resolution through spacer-based pattern multiplication. This parameter transformation achieves the required fine pitch without needing ultra-high-precision lithography equipment, thereby reducing manufacturing costs while maintaining the hexagonal close-packed arrangement precision.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250201561A1Method for manufacturing semiconductor device and pattern forming method
Publication Date: 2025.06.19 KIOXIA CORP
  • US20250201561A1 patent drawing
  • US20250201561A1 patent drawing
  • US20250201561A1 patent drawing

AI summary

A first hole pattern is transferred to a first hard mask layer to form a first hard mask pattern having a second hole pattern, a first spacer layer is formed on a side wall of the second hole pattern and the first hard mask pattern is removed to form a first spacer pattern being cylindrical and arranged at a position of the second hole pattern, a second spacer layer covering an upper surface of the second hard mask layer outside the first spacer pattern is formed, and a second spacer pattern having a third hole pattern is formed by removing the second spacer layer overlapping a first region consisting of a minimum distance connecting center points of the first spacer pattern, to form a fourth hole pattern including the second hole pattern included in the first spacer pattern and the third hole pattern included in the second spacer pattern.