Disposable Spacer Layer for Reducing GIDL in MOS Transistors
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Solution Overview
Problem
Current semiconductor manufacturing methods fail to effectively reduce gate-induced drain leakage (GIDL) in MOSFETs without increasing the transistor's size or affecting nearby transistors, as scaling down feature dimensions leads to higher current leakage and power consumption.
Innovation Solution
A method involving the deposition of a disposable spacer layer during semiconductor processing, which acts as an additional implant mask to increase the lateral spacing between the gate and source/drain regions, thereby reducing GIDL, and is easily removable to ensure good electrical contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature dimensions are scaled down to increase integration density, then integration density and speed are improved, but gate-induced drain leakage (GIDL) increases causing higher power consumption
Solution Approach 1:
The patent segments the doping process into multiple stages with different dopant concentrations. A first doping concentration is applied to form initial source/drain regions, followed by a second doping concentration to adjust the threshold voltage. This segmentation allows independent optimization of GIDL reduction and threshold voltage control without requiring overall process changes that would affect nearby transistors.
Solution Approach 2:
The patent applies local quality by using a disposable spacer layer that is selectively removed only in regions where GIDL reduction is needed. The spacer layer provides localized protection during doping, creating different doping profiles in different regions of the same transistor. This allows GIDL reduction in specific areas while maintaining original characteristics in other areas, including nearby transistors.
2Loss of energy
If a disposable spacer layer is deposited to reduce GIDL, then GIDL is reduced by about 1.1 log A, but the manufacturing process complexity increases
Solution Approach 1:
The patent employs a disposable spacer layer made of a temporary material that is deposited, used as a masking layer during doping, and then completely removed. This disposable element simplifies the overall process by providing a straightforward mechanism for GIDL reduction without requiring permanent structural changes or complex multi-step patterning sequences. The spacer layer's temporary nature allows it to be easily discarded after serving its protective function.
Solution Approach 2:
The patent utilizes parameter changes by varying the thickness of the disposable spacer layer to control the extent of GIDL reduction. By adjusting spacer thickness, the doping profile can be precisely controlled to achieve optimal GIDL reduction while maintaining drive current and threshold voltage characteristics. This parameter-based control provides a simple yet effective way to manage GIDL without increasing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces GIDL by about 1.1 log A, allowing for the integration of low-leakage 5V P-MOSFETs on processes designed for 1.8V and 3.3V MOSFETs without affecting drive current or threshold voltage, and can be customized for various transistor types.
Implementation Method 1
acts as an additional implant mask to increase the lateral spacing between the gate and source/drain regions
Implementation Method 2
easily removable to ensure good electrical contact
Data Source
AI summary
Improved semiconductor topographies and methods are provided herein for reducing the gate induced drain leakage (GIDL) associated with MOS transistors. In particular, a disposable spacer layer is used as an additional mask during implantation of one or more source/drain regions. The physical spacing between the gate and the source/drain regions of a MOS transistor (i.e., the gate/drain overlap) can be varied by varying the thickness of the disposable spacer layer. For example, a larger spacer layer thickness may be used to decrease the gate/drain overlap and reduce the GIDL associated with the MOS transistor. The disposable spacer layer is completely removed after implantation to enable electrical contact between the source/drain regions and subsequently formed source/drain contacts. A method is also provided herein for independently customizing the amount of current leakage associated with two or more MOS transistors.