Spacer Layer Mitigates TDDB in Replacement Gate Stacks
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Solution Overview
Problem
The miniaturization of integrated circuits (ICs) reduces the spacing between transistor gates and source/drain contacts, making the interlayer dielectric susceptible to leakage current, which can lead to time-dependent dielectric breakdown (TDDB) failures, and existing solutions are costly and complicate the fabrication process.
Innovation Solution
Introducing a spacer layer during the replacement metal gate process to increase the thickness of the dielectric stack between the transistor gate and source/drain contacts, reducing leakage currents by requiring the current to traverse a thicker dielectric material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the spacing between transistor gate and source/drain contacts is reduced to enable miniaturization, then IC dimension is improved, but the interlayer dielectric becomes susceptible to leakage current and TDDB failures
Solution Approach 1:
The patent introduces a spacer layer that adds vertical dimension to the dielectric structure. By depositing an additional dielectric layer (such as silicon nitride or silicon oxynitride) over the existing interlayer dielectric, the solution increases the effective dielectric thickness in the vertical direction, thereby mitigating leakage current issues caused by reduced horizontal spacing between gate and source/drain contacts.
Solution Approach 2:
The patent employs composite dielectric structures by combining multiple dielectric materials with different properties. The spacer layer uses materials such as silicon nitride (SiN) or silicon oxynitride (SiON) that have higher dielectric strength and lower leakage current characteristics compared to the base interlayer dielectric material, creating a composite structure that enhances overall reliability.
2Reliability
If a spacer layer is introduced to increase dielectric thickness, then leakage current is reduced, but fabrication process complexity increases
Solution Approach 1:
The patent merges the spacer layer formation process with the existing metal gate replacement process. The spacer layer is deposited and patterned in conjunction with other fabrication steps already present in the manufacturing flow, such as combining it with dielectric deposition and etching steps that are part of the standard process, thereby minimizing additional process complexity.
Solution Approach 2:
The spacer layer serves multiple functions simultaneously: it increases dielectric thickness to reduce leakage current, provides mechanical support, and can be integrated with the metal gate replacement process. This multi-functionality reduces the need for separate dedicated processes, thereby limiting the increase in fabrication complexity.
3Reliability
If existing solutions are implemented to prevent TDDB failures, then transistor reliability is improved, but manufacturing cost increases
Solution Approach 1:
The spacer layer formation utilizes materials and processes that are already part of the standard fabrication toolkit. By using dielectric materials like silicon nitride or silicon oxynitride that can be deposited through existing CVD or PECVD equipment, and by integrating the process with standard patterning and etching steps, the solution avoids requiring expensive new equipment or materials.
Solution Approach 2:
The spacer layer uses conventional dielectric materials that are cost-effective and readily available in semiconductor manufacturing. Materials such as silicon nitride and silicon oxynitride are standard in the industry and can be deposited using existing equipment, avoiding the need for expensive specialized materials or processes.
Data Source
AI summary
The present disclosure describes an exemplary replacement gate process that forms spacer layers in a gate stack to mitigate time dependent dielectric breakdown (TDDB) failures. For example, the method can include a partially fabricated gate structure with a first recess. A spacer layer is deposited into the first recess and etched with an anisotropic etchback (EB) process to form a second recess that has a smaller aperture than the first recess. A metal fill layer is deposited into the second recess.