Method of forming patterns of semiconductor device

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Solution Overview

Problem

In semiconductor device manufacturing, existing methods face challenges in forming fine patterns with narrow widths and intervals that exceed the resolution limit of photolithography processes, leading to issues like halation and reduced contact area and increased contact resistance between conductive lines and vias.

Innovation Solution

A method involving the formation of insulating films, mask layers, and spacer patterns to create composite mask patterns, allowing for the etching of insulating patterns with narrow openings and wide openings, followed by filling and polishing to achieve conductive lines with varying widths, thereby addressing the resolution limitations and halation issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If photolithography process is used to form fine patterns, then manufacturing process is simple, but pattern width and interval cannot exceed resolution limit

Engineering Contradiction:
Improvepattern widthVSAvoidpattern formation process
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The pattern formation process is divided into multiple stages: first forming a mandrel pattern, then forming spacers on the mandrel, and finally forming the final pattern. This multi-stage segmentation allows achieving ultra-fine patterns beyond photolithography resolution limits by using each stage for a specific function.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from two-dimensional photolithography patterning to three-dimensional spacer-based patterning. By forming vertical spacers on the mandrel structure, the pattern dimensions are defined by the spacer thickness rather than optical resolution, enabling sub-lithographic feature sizes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If narrow openings are formed to increase pattern density, then contact area between conductive lines and vias is reduced, but contact resistance increases

Engineering Contradiction:
Improvepattern densityVSAvoidcontact resistance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The spacer width is locally optimized to provide adequate contact area while maintaining high pattern density. The spacer structure creates a localized expansion in the conductive line width at via contact regions, ensuring sufficient contact area and low contact resistance even in high-density patterns.

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If photolithography resolution limit is exceeded to form finer patterns, then halation occurs, but pattern quality deteriorates

Engineering Contradiction:
Improvepattern finenessVSAvoidhalation
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The mandrel pattern is formed first as a preliminary structure that defines the eventual pattern location and dimensions. The spacer is then formed on this pre-defined mandrel, allowing the final pattern dimensions to be controlled by the spacer thickness rather than photolithography resolution, thereby avoiding halation effects.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20240194521A1Method of forming patterns of semiconductor device
Publication Date: 2024.06.13 SAMSUNG ELECTRONICS CO LTD
  • US20240194521A1 patent drawing
  • US20240194521A1 patent drawing
  • US20240194521A1 patent drawing

AI summary

A method of forming a pattern of a semiconductor device, the method comprising forming an insulating film on a substrate having a first region and a second region, sequentially forming a lower mask layer and an upper mask layer on the insulating film, forming a line-shaped hard mask pattern having a plurality of narrow openings having the same width in the first region and the second region, respectively, on the upper mask layer, forming line-shaped spacers on sidewalls of the opening of the line-shaped hard mask pattern, forming a composite mask pattern composed of the spacer and a pattern having a first width among the line-shaped hard mask pattern by removing a pattern having a second width among the line-shaped hard mask patterns, the second width being smaller than the first width.