Spacer Passivation for High Aspect Ratio Etching in 3D NAND
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Solution Overview
Problem
The fabrication of three-dimensional vertical NAND devices faces challenges such as etch profile variation, hard mask erosion, and critical diameter non-uniformity due to reactive ion etching of high aspect ratio memory openings, limiting the number of controllably etched memory layers within acceptable process variations.
Innovation Solution
The use of sidewall spacer passivation to improve etch profiles in multilayer stacks, where a conformal or non-conformal spacer is deposited to protect sidewalls from over-etching, allowing for controlled etching of memory openings and widening of the critical diameter, particularly in the lower portions of the openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If reactive ion etching is used to etch high aspect ratio memory openings in multilayer stacks, then memory openings can be formed vertically through the stack, but etch profile variation, hard mask erosion, and critical diameter non-uniformity occur
Solution Approach 1:
A spacer layer is deposited conformally on the sidewalls of the memory opening as an intermediary protective layer. This spacer acts as a mediator that prevents direct contact between the etch plasma and the hard mask sidewalls, thereby preventing hard mask erosion and maintaining etch profile uniformity throughout the high aspect ratio opening
Solution Approach 2:
The spacer layer is deposited preliminarily before the main etching process to prepare the sidewall protection. This preliminary action ensures that the hard mask is protected from erosion during subsequent etching steps, maintaining critical diameter uniformity from the beginning of the etch process
2Productivity
If traditional etching methods are used without sidewall protection, then the etching process can be completed faster, but etch profile variation and critical diameter non-uniformity increase
Solution Approach 1:
The conformal spacer layer serves as a protective intermediary that allows faster etching rates to be used without sacrificing critical diameter uniformity. The spacer prevents etch profile variation by shielding the hard mask sidewalls from plasma exposure during the accelerated etching process
3Quantity of substance
If the opening is etched deeper to increase memory cell density, then vertical scaling is achieved, but etch profile variation and process control difficulty increase
Solution Approach 1:
The spacer layer acts as a protective intermediary that enables deeper etching to increase memory cell density while maintaining etch profile control. By preventing hard mask erosion during the extended etching process, the spacer ensures uniform critical diameter even at greater depths
Solution Approach 2:
The solution transitions from controlling etch depth in one dimension to controlling sidewall protection in another dimension. The conformal spacer provides dimensional control by maintaining consistent thickness around the opening perimeter, enabling precise control of the etched profile throughout the vertical depth
Data Source
AI summary
A method of making a semiconductor device includes forming a stack of alternating layers of a first material and a second material over a substrate, etching the stack to form at least one opening extending partially through the stack and forming a masking layer on a sidewall and bottom surface of the at least one opening. The method also includes removing the masking layer from the bottom surface of the at least one opening while leaving the masking layer on the sidewall of the at least one opening, and further etching the at least one opening to extend the at least one opening further through the stack while the masking layer remains on the sidewall of the at least one opening.