Spacer-Based Pattern Fabrication for Sub-100nm Pitch
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor lithography techniques, such as 193 nm lithography, face limitations in miniaturizing pattern pitch due to low resolution, poor photoresist quality, and high manufacturing costs, making it challenging to reduce feature sizes below 100 nm and increasing integration density in integrated circuits.
Innovation Solution
A method involving the formation of a patterned hard mask layer, spacer formation on its sidewalls, and subsequent etching processes to create a patterned material layer with equal width and spacing, utilizing different etch selectivities and materials like polysilicon, dielectric, and metal layers, and oxides or nitrides, to miniaturize the pattern pitch without requiring advanced tools or materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If 193 nm lithography is used to improve resolution, then pattern quality may be improved, but manufacturing cost increases and photoresist pattern quality deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the pattern formation process into multiple stages: first forming a mandrel pattern, then using spacer deposition and removal cycles to progressively subdivide the pitch. This multi-step self-aligned process achieves sub-100nm dimensions without requiring higher-resolution lithography, thereby avoiding the increased manufacturing costs associated with 193 nm lithography while maintaining pattern quality
Solution Approach 2:
The patent transitions from two-dimensional lithographic patterning to three-dimensional spacer-based patterning. By depositing conformal spacers on mandrels and using vertical dimension control (spacer thickness) to define horizontal pattern dimensions, the method achieves resolution beyond the lithographic limit without upgrading the lithography system, thus avoiding increased manufacturing costs
2Manufacturing precision
If lithography with shorter wavelength is used to reduce pattern pitch, then resolution is improved, but manufacturing cost and system complexity increase
Solution Approach 1:
The patent introduces spacers as intermediary structures that mediate between the lithographically-defined mandrels and the final target pattern. The spacers serve as self-aligned masks that define the final pattern dimensions through their thickness rather than through direct lithographic imaging, thereby achieving sub-100nm pitch without requiring complex short-wavelength lithography systems
Solution Approach 2:
The patent performs preliminary pattern formation by creating mandrels with spacing greater than the final target pitch. The actual fine-pitch pattern is then defined by the subsequently deposited spacers, which are formed by conformal deposition processes that do not require high-resolution lithography. This preliminary action allows the use of simpler, longer-wavelength lithography tools
3Ease of manufacture
If 248 nm lithography is used to fabricate patterns, then manufacturing cost is reduced, but pattern width cannot be extended below 100 nm
Solution Approach 1:
The patent employs self-aligned spacer formation where the spacers automatically position themselves relative to the mandrels through conformal deposition. The spacer thickness, controlled by deposition parameters rather than lithographic resolution, defines the final pattern width. This self-service mechanism allows 248 nm lithography to produce sub-100nm patterns without requiring resolution enhancement techniques, maintaining low manufacturing cost while achieving high precision
Solution Approach 2:
The patent changes the controlling parameter for pattern width from lithographic exposure parameters (wavelength, numerical aperture) to deposition parameters (spacer thickness, conformal coverage). By controlling spacer thickness through atomic layer deposition or chemical vapor deposition processes, the method achieves sub-100nm precision using 248 nm lithography without resolution enhancement techniques, maintaining cost-effectiveness
4Device complexity
If photoresist layer is used to determine width and spacing, then lithography process is simple, but pattern pitch cannot be reduced below 100 nm
Solution Approach 1:
The patent introduces spacers as intermediary structures that decouple the lithographic patterning step from the final pattern dimension definition. The lithography process only needs to create mandrels with relaxed pitch requirements, while the spacer deposition process defines the final sub-100nm dimensions. This intermediary approach maintains simple lithography processes while achieving high precision
Solution Approach 2:
The patent moves the pattern dimension control from the two-dimensional lithographic plane to the vertical deposition dimension. By controlling spacer thickness through conformal deposition, the final horizontal pattern dimensions are determined by vertical process control rather than lateral lithographic resolution, enabling sub-100nm pitch with simple lithography
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively miniaturizes the pattern pitch, enabling increased integration density in integrated circuits while reducing manufacturing costs by using existing lithographic techniques, achieving pattern widths and spacings of 100 nm or less, and improving pattern quality.
Implementation Method 1
a spacer material layer is formed on the material layer, wherein the spacer material layer conformably covers the patterned hard mask layer
Implementation Method 2
an anisotropic etching process is performed to remove a portion of the spacer material layer
Implementation Method 3
the spacer, the patterned hard mask layer and the material layer have different etch selectivities
Data Source
AI summary
A method for fabricating a patter is provided as followed. First, a material layer is provided, whereon a patterned hard mask layer is formed. A spacer is deposited on the sidewalls of the patterned hard mask layer. Then, the patterned hard mask layer is removed, and an opening is formed between the adjacent spacers. Afterwards, a portion of the material layer is removed to form a patterned material layer by using the spacer as mask.