Spacer Patterning for Smaller Semiconductor Features Without Collapse
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Solution Overview
Problem
Conventional photolithography processes face challenges in reducing critical size due to pattern bending or collapse caused by large height-to-width ratios, necessitating a more effective patterning method for semiconductor devices.
Innovation Solution
A method involving the formation of core and spacer layers with treatment processes to enhance spacer properties, preventing bending or collapse, and transferring patterns from spacers to target layers using self-aligned double and quadruple patterning techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional photolithography is used to reduce critical size, then resolution is improved, but pattern bending or collapse occurs due to large height-to-width ratio
Solution Approach 1:
The patterning process is divided into multiple stages: first forming a mandrel pattern, then using spacer layers to define final patterns. This segmentation allows each stage to be optimized independently, preventing pattern collapse while achieving high resolution
Solution Approach 2:
Spacer layers are formed and treated before the final patterning step. The preliminary treatment process modifies spacer properties in advance to prevent bending or collapse during subsequent etching and pattern transfer operations
2Manufacturing precision
If spacer layers are formed with high aspect ratio to achieve smaller features, then manufacturing precision is improved, but spacer bending or collapse increases
Solution Approach 1:
The treatment process changes physical or chemical parameters of the spacer layer material, such as density, cross-linking, or crystallinity, to enhance mechanical strength and resist bending or collapse during high aspect ratio formation
Solution Approach 2:
The spacer layer is formed using composite material structures or treatments that combine multiple properties, achieving both the required dimensional precision for small features and sufficient structural strength to prevent collapse
3Productivity
If double-patterning method is used to overcome optical limit, then integration is improved, but process complexity increases
Solution Approach 1:
The patterning process uses nested structures where spacers are formed around mandrels, then mandrels are removed and new spacers are formed around the first spacers. This nested approach systematically increases integration density while managing process complexity through repeated application of the same basic steps
Data Source
AI summary
A method of manufacturing a semiconductor device includes the following. A core material layer and a patterned mask layer are formed above a target layer. A first spacer layer is formed and a first treatment process is performed to form a treated first spacer layer. A first removal process is performed on the treated first spacer layer and the patterned mask layer to form multiple first spacers. The core material layer is patterned to form a core layer using the first spacers as a mask. A second spacer layer is formed and a second treatment process is performed to form a treated second spacer layer. A second removal process is performed on the treated second spacer layer and the core layer to form multiple second spacers. A pattern of the second spacers is transferred to the target layer to form a patterned target layer.